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st75c530 ST75C540 super integrated devices with dsp, afe & memories for telephony, modem, fax over internet & pots lines february 1999 tqfp80 (14 x 14 x 1.4mm) (full thin plastic quad flat pack) order code : st75c530fp-a ST75C540fp-a summarized features (for detailed features, see page 4) . single chip fax up to 14.4kbps (v.17) . full duplex data modem up to 14.4kbps (v.32bis) . digital answering machine : - 4.8kbps vocoder - variable playback speed (+50% to -50%) - adpcm 32, 34, 16kbps vocoder . full-duplex digital speakerphone with echo cancellation . programmable ring detection . 16 programmable tone detectors for clid and scwid . dtmf detection . versatile host interfaces . 16 general purpose i/o ports . 2 relay drive outputs . single 5v power supply . typical active power consumption : 650mw (st75c530), 750 mw (ST75C540) . low power mode < 30mw . 80-pin tqfp package (14mm x 14mm) description st75c530 and ST75C540 are two super-inte- grated devices including dsp, modem and audio analog front ends and memories for telephony, modem and fax applications. these devices can be used for classical applica- tions over pots lines or over internet. the super integration technology allows a signifi- cant cost reduction on bill of materials for equip- ment like high-end phones, internet phones, phone-fax, internet fax, ... the devices are used with a host processor through a dual port ram allowing the use of any kind of microcontroller (risc, cisc, general pur- pose 8-bit m c, ...). the embedded software includes : - handset with listening group capability, - full duplex handsfree, - voice coder/decoderat 4.8kbpsfor staticanswer- ing machine applications and adpcm 16kbps, 24kbps and 32kbps for high quality message recording, - tone and dtmf generators, - tone and dtmf detectors, - fax up to 14.4kbps, - data-modem up to 14.4kbps (ST75C540 only). the dsp sofware is extensively user configurable allowing specific functions to be supported like caller identifier (clid) and second call waiting identifier (scwid). the dsp software includes a transparent mode allowing the host controller to access directly the modem analog front end and the audio afe through the dual port ram. this is very useful for hostprocessing modem solutions (or soft modem) where the modulation and the demodulation (v.34, v.90) are done by the application main processor. in transparent mode, the embedded dsp can be used simultaneously with the same samples. the transparentmode for audio afe is provided to play audio files or to record voice and/or audio. 1/84
contents page i detailed features ................................................. 4 ii pin description .................................................... 5 ii.1 pin connections. . . . ................................................ 5 ii.2 host interface. .................................................... 6 ii.3 analog interface . ................................................. 6 ii.4 general purpose io and relay . . . . ................................. 6 ii.5 miscellaneous . .................................................... 7 ii.6 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . ........................... 7 iii block diagrams .................................................... 8 iii.1 analog interface . ................................................. 8 iii.2 internal block diagram . ........................................... 8 iv electrical specifications ......................................... 9 iv.1 maximum rating s...................... ............................. 9 iv.2 recommended operating conditions . . . . . . . . . ...................... 9 iv.3 digital interface. . . . . . . . . . . . . . . . . . . . . . ............................. 10 iv.4 modem analog interface . . . . ....................................... 11 iv.5 audio analog interface . ........................................... 11 iv.6 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . ......................... 12 v functional description ............................................ 13 v.1 system architecture . . . . .......................................... 13 v.2 modes of operation. . . . . . . . . . . . . . . . . . . . . . . ......................... 13 v.3 operations. . . . . . . . . . . . . . . . . . . . . . . . ................................. 13 v.3.1 modem transmitter description . . . . ....................................... 13 v.3.2 modem receiver description . . . . . . . . . . . . . . . . . . . . . . . ...................... 13 v.3.3 tone generator description . . . . .......................................... 13 v.3.4 tone detector description . .............................................. 13 v.3.5 v.21 channel 2 flag detector description . .................................. 13 v.3.6 hdlc description . . . . . . . . . . . . . . . . . . . . . . . . . . . ........................... 13 v.3.7 uart description . . . . . . . . . . . . . . . . . . . . . . . . . . . ........................... 13 v.3.8 dtmf detector description. .............................................. 13 v.3.9 ring detector . . . . . . . . . . . . . . . . . . . . . . . . ................................. 13 v.3.10 vocoder description . ................................................. 14 v.3.11 voice activity detector (vad) . . . . . . . . . . . . . . . . . . . . . . . ...................... 14 v.3.12 telephony functions. . . . ................................................ 15 v.3.13 low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . ........................... 18 v.3.14 reset. . . . . . . . . . . . . . .............................................. .... 18 v.4 modem interface . . . . . . . . . . . . . . . . . . . . . . ............................. 18 v.4.1 analog interface . . . . ................................................... 18 v.4.2 general i/o and relay interface . . . . ....................................... 18 v.4.3 crystal. ........................................................... ... 19 v.4.4 typical application schematic. . . . . . . . . . . . . . . . . . . . . . . ...................... 19 v.4.5 host interface . . . . . . . . . . . . . . . . . . . . . . . . ................................. 19 vi user interface ..................................................... 21 vi.1 dual port ram description . ........................................ 21 vi.2 command set . . . . ................................................... 25 vi.3 command set short form . . . . . . . . . . . . .............................. 26 vi.4 status - reports . . . . . . . . . . . . . . . . . . . . . . ............................. 27 vi.5 data exchanges. . . . ................................................ 27 st75c530 - ST75C540 2/84
vii command set description .......................................... 28 viii status description ................................................ 43 viii.1 command acknowledge and report . . . . . . .......................... 43 viii.2 modem status . . . . . . . . . . . . . . . . . . . . . . . . . . . ........................... 44 ix tone detectors .................................................... 53 ix.1 overview. .......................................................... 53 ix.2 description . ....................................................... 53 ix.3 example. . . . . . . . . . . . . . . . . . . . . . . . .................................... 59 x parallel data exchange ........................................... 60 x.1 overview. .......................................................... 60 x.2 transmit buffer . . . . . . . . . . . . . . . . . . . . . . ............................. 60 x.3 receive buffer . .................................................... 61 x.4 interruption . . . . ................................................... 61 x.5 data format . . . . ................................................... 61 x.6 form command . .................................................... 63 xi transmitting data in parallel mode ............................... 64 xi.1 description . ....................................................... 64 xi.2 modem flow chart . . . . ............................................. 65 xi.3 host flow chart . . . . . . . . . . . . . . . . . . . . . . ............................. 65 xi.4 error detection . . . . . . . . . . . . . . . . . . . . . . ............................. 66 xi.5 synchronous mode . . . . . . . . . . . . . . . . . . . . . . . ......................... 66 xi.6 hdlc mode. . . . ...................................................... 67 xi.7 uart mode description. . . . . . . . . . . . . . . . . . . . . . . ...................... 69 xii receiving in parallel mode ........................................ 70 xii.1 description . ....................................................... 70 xii.2 modem flow chart . . . . ............................................. 70 xii.3 host flow chart . . . . . . . . . . . . . . . . . . . . . . ............................. 70 xii.4 error detection . . . . . . . . . . . . . . . . . . . . . . ............................. 71 xii.5 synchronous mode . . . . . . . . . . . . . . . . . . . . . . . ......................... 72 xii.6 hdlc mode. . . . ...................................................... 72 xii.7 uart mode. . . . ...................................................... 74 xiii vocoder data exchange ........................................... 74 xiii.1 overview. .......................................................... 74 xiii.2 vocoder buffer. . . . ................................................ 74 xiii.3 transmit (decoder) . . . . . . . . . . . . . . . . . . . . . . . ......................... 74 xiii.4 receive (coder) . . . . ................................................ 75 xiv transparent mode data exchange ................................. 75 xv default call progress tone detectors ........................... 76 xvi default answer tone detectors .................................. 76 xvii electrical schematics ............................................. 77 xviii pcb design guidelines .............................................. 78 xix appendix a : modes of operation . .................................. 78 xx package mechanical data ......................................... 83 st75c530 - ST75C540 3/84
i - detailed features single chip fax - itu-t v.17, v.29, v.27ter, v.21 with fax support - v.17, v.29 (t104), v.27ter short trains, v.33 half-duplex - v.21 flag detection and 4 tone detection during high speed reception modes - v.21 flag detection, dtmf detection and 4 tone detection duringv.21 channel 2 reception modes - programmable call progress and call waiting detection - parallel data handling - hdlc and uart framing support - 1700hz and 1800hz carrier - full implementation of the v.17, v.33, v.29 and v.27 handshakes - 0 to -15dbm programmable transmit power - 0 to -47dbm receiver dynamic range (st75c530) 0 to-45dbm receiver dynamic range (ST75C540) full duplex data modem - itu-t v.32bis, v.32 (14400, 12000, 9600, 7200, 4800bps) (*) - maximum round trip delay : 1.2s (satellite hops) (*) - up to 10hz of phase roll on far end echo (*) - itu-t v.22bis, v.22 (2400, 1200bps) (*) - v.32bis/v.32/v.22bis/v.22automode (*) - itu- v.23, v.21, bell 103 full-duplex, bell202 demodulator - -10 to -25dbm programmable transmit power - -10 to -38dbm receiver dynamic range (*) - hdlc and uart framing support - train based on quality line sampling (*) (*) ST75C540 only digital answering machine - low bit rate speech coder (4800bps) - variable playback speed (+50% to -50%) - aram compatibility (error correction) - adpcm 32, 24, 16kbps - line echo cancellation - voice activity detector - concurrent dtmf and tone detection handset mode - rx and tx agc versus line current for line losses compensation comply with most of country regulations - dynamic limiter in transmit path to prevent distortion - two way conversation recording hands-free mode - full duplex speakerphone using lms adaptative filtering including line echo cancellation and acoustic echo cancellation - rx and tx agc versus line current for line losses compensation comply with most of country regulations - dynamic limiter in transmit path to prevent distortion - loudspeaker volume control - two way conversation recording extended modes of operations - programmable ring detection - 16 programmable tone detectors - tone and dtmf generators - caller id reception - transparent mode allowing direct transfer of mo- dem afe and audio afe samples to and from host processor for soft modem applications and sound files playing - dtmf detection - wide dynamic range (>48db) versatile interfaces - parallel 128 x 8-bit dual port ram - general purpose 16 i/o ports - 2 relay drive outputs - full diagnostic capability - dual 8-bit dac for constellation display single 5v power supply - typical active power consumption : 650mw (st75c530), 725mw (ST75C540) - low power mode < 30mw st75c530 - ST75C540 4/84
65 66 67 68 69 70 71 72 73 74 75 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 26 27 28 29 30 31 32 33 34 35 36 21 22 23 24 25 76 77 78 79 80 17 18 19 20 37 38 39 40 44 43 42 41 61 62 63 64 gio10 dv dd4 dgnd4 gio07 gio06 gio05 gio04 gio03 gio02 dv dd3 dgnd3 gio01 gio00 ring relay1 relay0 rgnd int/mot sintr scs spk1n agndta v refn v refp spk1p v cm agndra mic1 mic2 mic3 rxa av ddm agndm txa2 txa1 eyex eyey dgnd6 dv dd6 dgnd1 dv dd1 sd0 sd1 sd2 sd3 sd4 sd5 sd6 sd7 dgnd2 dv dd2 sr/w sds sa0 sa1 sa2 sa3 sa4 sa5 sa6 av dda spk2p spk2n spk3p spk3n reset test0 extall xtall dv dd5 dgnd5 xpll clkout gio17 gio16 gio15 gio14 gio13 gio12 gio11 75c53001.eps ii - pin description ii.1 - pin connections st75c530 - ST75C540 5/84
ii.2 - host interface the exchanges with the control processor proceed through a 128 x 8 dual port ram shared between the st75c530/540 and the host. the signals associated with this interface are : pin name type description sd0..sd7 i/o system data bus. 8-bit data bus used for asynchronous exchanges between the st75c530/540 and the host through the dual port ram. high impedance when exchanges are not active. sa0..sa6 i system address bus. 7-bit address bus for dual port ram, io and interrupt registers. sds (srd) i system data strobe. in motorola mode sds initiates the exchange, active low. in intel mode srd initiates a read exchange, active low. sr/w (swr) i system read/write. in motorola mode sr/w defines the type of exchange read/write. in intel mode swr initiates a write exchange, active low. scs i system chip select. active low. sintr od system interrupt request. open drain. active low. this signal isasserted by the st75c530/540 and negated by the host. reset i reset. active low. int/mot i select intel or motorola interface ii.3 - analog interface pin name type description txa1 o transmit analog output 1 txa2 o transmit analog output 2 rxa i receive analog input spk1p o speaker output 1, (differential positive), must be connected through amplifier to the loudspeaker. spk1n o speaker output 1, (differential negative) spk2p o speaker output 2, (differential positive), must be connected through amplifier to the handset loudspeaker. spk2n o speaker output 2, (differential negative) spk3p o speaker output 3, (differential positive) spk3n o speaker output 3, (differential negative) mic1 i microphone input 1 mic2 i microphone input 2 mic3 i microphone input 3 v cm i/o analog common voltage (nominal +2.5v). this input must be decoupled with respect to agnd. v refn i analog negative reference (nominal 1.25v). this input must be decoupled with respect to v cm . v refp i analog positive reference (nominal 3.75v). this input must be decoupled with respect to v cm . ii.4 - general purpose io and relay pin name type description gio[0,7] i/o general purpose i/o pins, can be independently selected as input or output. gio[10,17] i/o general purpose i/o pins, can be independently selected as input or output. relay0, relay1 od relay outputs, open drain, active low. can sink -10ma to rgnd. ring i ring detect signal. active low. if the st75c530/540 is in low power mode, a low level will awake the chip. this input is a schmidt's trigger. rgnd pwr relay digital ground. to connect to gnd. ii - pin description (continued) st75c530 - ST75C540 6/84
ii.5 - miscellaneous pin name type description eyex o constellation x analog coordinate eyey o constellation y analog coordinate xtal o internal oscillator output. left open if not used. extal i internal oscillator input, or external clock input. xpll i reserved for future use, must be connected to digital ground. clkout o output clock, extal/2 (not available in low power mode). test0 i test pin for normal operation, must be connected to digital ground. note : the nominal frequency of the crystal oscillator is 44.2368mhz with a precision better than 100ppm. ii.6 - power supply symbol nber parameter dv dd 6 digital +5v. dgnd 6 digital ground. av dd 2 analog +5v. agnd 3 analog ground. ii - pin description (continued) st75c530 - ST75C540 7/84
15 adc mute dac line hybrid txa1 txa2 rxa adc 14 11 10 mic3 8 mic1 9 mic2 79 spk2 78 mute 77 spk3 76 mute 2 spk1 1 mute [0..-30]db step 3db dac st75c530/540 75c53002.eps iii - block diagrams iii.1 - analog interface iii.2 - internal block diagram dual port ram gio and relay eye dac prom 26624 instructions analog front end time base osc st18932 dsp (24mips) ram 6144 words rom 16368 words autotest 1024 instructions autotest 1024 instructions eyex eyey xtal eyey clkout extal ring relay0 relay1 pins 48-49 pins 52 to 57 gio0[0..7] pins 60 to 67 gio1[10..17] pins 22 to 29 sd[0..7] pins 34 to 40 sa[0..6] sintr instruction bus data bus 45 46 16 17 68 72 73 47 42 st75c530/540 75c53003.eps st75c530 - ST75C540 8/84
iv - electrical specifications iv.1 - maximum ratings (agnd = dgnd = rgnd = 0v, all voltages with respect to 0v) symbol parameter value unit av dd analog power supply -0.3, 6.0 v dv dd digital power supply -0.3, 6.0 v i i input current per pin (except supply pins and relay0 and relay1) -10, +10 ma i o output current per pin (except supply pins and relay0 and relay1) -20, +20 ma i o2 output current per pin relay0 or relay1 (respect to rgnd) -40, 0 ma v ia analog input voltage -0.3, av dd + 0.3 v v id digital input voltage -0.3, dv dd + 0.3 v v idgpio digital input voltage at gpio 5.25 v t oper operating temperature 0, +70 c t stg storage temperature - 40, +125 c p tot maximum power dissipation 1500 mw warning : operation beyond these limits may result in permanent damage to the device. normal operation is not guaranted at these extremes. iv.2 - recommended operating conditions (agnd = dgnd = rgnd = 0v, all voltages with respect to 0v) symbol parameter min. typ. max. unit v dd supply voltage 4.75 5 5.25 v i dd supply current st75c530 ST75C540 130 145 150 165 ma ma p dlp low power 30 mw p d power st75c530 ST75C540 650 725 790 866 mw mw v cm common mode voltage output (refer to av dd /2) -5 +5 % i cm common mode current (see note 1) 100 m a note 1 : dc current only. if dynamic load exists, the v cm output must be buffered or the performances of adcs and dacs will be degraded. st75c530 - ST75C540 9/84
iv.3 - digital interface (av dd =dv dd = 5v, agnd = dgnd = rgnd = 0v) except xtal, extal, ring. symbol parameter min. typ. max. unit v ih high level input voltage 2.2 v v il low level input voltage -0.3 0.8 v v oh high level output voltage (i load = -2ma, i load = -4ma for sd[7..0]) 2.4 v v ol low level output voltage (i load = 2ma, i load = 4ma for sd[7..0]) 0.4 v i leak input leakage current -10 10 m a i ol low level output current (except relay0 and relay1, and sintr) (0 < v ol ST75C540 10/84
iv.4 - modem analog interface av dd =dv dd =5v,t amb =25 o c measurement bandwidth is flat from 100hz to 4800hz ;load impedance 10k w , 20pf for differential output (txa1/txa2) : 0dbr = 1.77v rms 1khz sinwave (equivalent to 5v pp ). for single input (rxa) : 0dbr = 886mv rms 1khz sinwave (equivalent to 2.5v pp ). symbol pin name parameter min. typ. max. unit rxrin rxa input impedance 100 k w rxmac maximum ac input voltage = 0dbr 2.5 v pp rxdc dc reference voltage 2.5 v rxsndr signal to (noise + distortion), at -6dbr 75 db rxin idle noise -81 dbr rxov dc offset voltage (input = v cm ) -50 100 mv txadrl txa1/txa2 minimum differential load 10 k w txacl maximum differential load 20 pf txarout output impedance 100 w txamac maximum ac differential output = 0dbr 5 v pp txadc dc reference voltage 2.5 v txaov dc offset voltage -200 200 mv txasndr signal to (noise + distortion), at -6dbr 79 db txain idle noise -85 dbr iv.5 - audio analog interface av dd =dv dd =5v,t amb =25 o c measurement bandwidth is flat from 100hz to 4800hz ;load impedance 10k w , 20pf for differential output (spk1n/spk1p, spk2n/spk2p, spk3n/spk3p) : 0dbr = 1.77v rms 1khz sinwave (equivalent to 5v pp ). for single input (mic1, mic2, mic3) : 0dbr = 886mv rms 1khz sinwave (equivalent to 2.5v pp ). symbol pin name parameter min. typ. max. unit rarin mic1, mic2, mic3 input impedance 100 k w ramac maximum ac input voltage = 0dbr 2.5 v pp radc dc reference voltage 2.5 v radis distortion at -6dbr 2 % rain idle noise -81 dbr raov dc offset voltage (input = v cm ) -50 50 mv tadrl spk1n/spk1p, spk2n/spk2p, spk3n/spk3p minimum differential load 10 k w tarout output impedance 100 w tamac maximum ac differential output = 0dbr 5 v pp tadc dc reference voltage 2.5 v taov dc offset voltage -200 200 mv tadis distortion at -6dbr 1 % tain idle noise -81 dbr iv - electrical specifications (continued) st75c530 - ST75C540 11/84
iv.6 - ac electrical characteristics iv - electrical specifications (continued) scs write cycle read cycle intel mode 132 142 5 out in 12 11 10 67 8 9 13 14 sa[0..6] sr/w sds wr rd sd[0..7] sintr gio(out), relay gio(in) motorola mode 75c53004.eps number description min. typ. max. unit 1 address and control set-up time 5 ns 2 address and control hold time 20 ns 3 write enable low state 45 ns 4 read enable low state 45 ns 5 access inhibition high state 70 ns 6 data set-up time 10 ns 7 data hold time 5 ns 8 gio output, relay, sintr clear delay 50 ns 9 gio output hold time 0 ns 10 read data access time 35 ns 11 data valid to tristate time 15 ns 12 data hold time 5 ns 13 gio input delay time 40 ns 14 gio input hold time 0 ns st75c530 - ST75C540 12/84
v - functional description v.1 - system architecture the chip allows the design of a completefax, data modem, hands-free telephone and answering machine system. a versatile dual port ram allows an easy interface with most micro-controllers. v.2 - modes of operation refer to appendix a for block diagrams. v.3 - operations v.3.1 - modem transmitter description the signal pulses are shaped in a dedicated filter further combined with a compromise transmit equalizer suited for transmission over strongly dis- torted lines. 3 different compromise equalizers are available and can be selected by software. v.3.2 - modem receiver description the receiver section handles complex signals and uses a fractionally spaced complex equalizer. it is able to cope with distant modem timing drifts up to 10 -4 as specified in the itu-t recommendations. it also compensates for frequency drift up to 10hz and for phase jitter at multiple and simultaneous frequencies. v.3.3 - tone generator description four tones canbe simultaneouslygeneratedby the st75c530/540. these tones are determined by their frequenciesand by the output amplitude level. a set of specific commands are also available for dtmf generation.any of the4 tonegeneratorscan be output independently either on the audio dac or the line dac. v.3.4 - tone detector description during tone (respectively tonecid) mode six- teen (respectively eight) tones can be simultane- ously detected by the st75c530/540. each of the tones to be detected is defined by the coefficients of a 4th order programmable iir. detection thresh- olds are programmable from -51dbm up to -6dbm. these primary detectors can detect tone up to 3.3khz (sampling rate 7.2khz in all modes). they also have a programmable internal wiring feature (see chapter ix). in all modes, except handset (handset) and full duplex v.32bis/v.32/v.22bis/v.22 (modem) modes, 4 additional tone detectors (each of them being a 4th order programmable iir) are concur- rently running. in handset mode only 2 additional tone detectors are available. detection thresholds are programmable from -51dbm up to -6dbm. this secondary programmable detector can detect tones up to 1.8khz by default set-up with a sam- pling rate at 4.8khz. but this 4 additional tone detectors can also detect tones up to 3.3khz with a sampling rate at 9.6khz. in order to avoid wrong detectgion, relative detectgion is also provided. v.3.5 - v.21 channel 2 flag detector description in all the receivefax modes, including v.21 chan- nel 2 mode, the st75c530/540 processes a v.21 flag a7eo detector, either in the idle state, the train sequence or the data mode. the detection time is 3 consecutive flags to detect and 1 byte to loose the detection. v.3.6 - hdlc description in all fax modes (modem), including v.21 chan- nel 2 mode, and also full duplex v.32bis/v.32/v.22bis/v.22 (modem) modes, a hdlc framing and deframing is supported by the st75c530/540. the number of transmitted flags can be programmed. v.3.7 - uart description in full duplex v.32bis/v.32/v.22bis/v.22 modem modes and tonecidv.23receive mode, a parallel uart is performed by the st75c530/540. this uart manage the break signal either at the trans- mit and the receive bit stream. the data format supported are 7 and 8 bit of data; even, odd or no parity, 1 or 2 stop bits. v.3.8 - dtmf detector description adtmf detector is includedin the st75c530/540, it allows detection of valid dtmf digits. a valid dtmf digit is defined as a dual tone with a total power higher than -43dbm, a duration higher than 40ms and a differentialamplitude within 8db. this dtmf detector is enabled in all modes except in fax modem, data modem and handset modes. it is also enabled in v.21 channel 2 receive mode. the dtmf thresholds and duration can be changed from they default value by overwriting dsp's ram locations. in the default setup, this detector is compliant with the net4 standard. the frequencydeviation can be changedby overwriting the default dtmf's filters coefficients. v.3.9 - ring detector this detector detects ring signal from 15hz to 68hz, it can be programmed to expand the mini- mum and maximum detection frequency up to 12hz (for min) and 144hz (for max). the detection time is equal to one period of the ring signal, and the loose time to the minimum between one period of the ring signal and the inverse of the minimum frequency. the associated sta_ring status is as figure 1. st75c530 - ST75C540 13/84
v.3.10 - vocoder description the vocoder mode allows the implementation of an answering machine function. in the coder mode the received samples from one of the two analog inputs, line or audio, are compressed by the st75c530/540 and written into the dual port ram vocoder buffer (vocxxx). at the same time the st75c530/540 is looking for an incoming dtmf tone and 4 different programmable tones. in the decoder mode the compressed samples are read from the dual port ram, decompressed and transmitted to one of the two analog output, line or micx. the st75c530/540 synthesises an estimation of its echo and subtracts it from the received signal. at the same time the st75c530/540 is looking for an incoming dtmf tone and 4 different tones. two algorithms of voice coding are implemented : - low bit rate speech coder (4800bps or 5300bps with forward error correction). - adpcm (st proprietary algorithm) at 32, 24 and 16kbps. if the low bit rate coder algorithm is selected the st75c530/540 has the capability to slow down or speed up the decoder flow up to 50%. this function allows a quick message listening if speed up is used, or at the opposite if slow down is used, an enhancement of the voice intelligibility. v.3.11 - voice activity detector (vad) in coder mode, for both of the voice coding algorithms, a voice activity detector is imple- mented while coding by the st75c530/540. the sta_109 bit and sta_109f bit reflect the state of the vad. after the conf command the vad is on (assume voice). the default time-out to detect si- lence is 2 secondsand the set-up time to detect the voice is 15ms. this vad information is also copied into the receive buffer status word msb (voc- sta bit7). this detector is fully programmable in level sensitivity (down to -60dbm), hysteresis, and various criteria. an optional silence suppressor is implemented in the coder section to suppress long silence in the incoming message. when enabled (conf_sup- sil equal 1) if a long silence is detected (sta_109 equal 0) the st75c530/540 stops generating buff- er interrupts. after that if a voice is again detected the st75c530/540 will resume the buffer interrupt mechanism. ring sta_ring t1 1/fmax prog. < t1 < 1/fmin prog. t2 < 1/fmax prog. t3 1/fmin prog. t2 t3 75c53005.eps figure 1 v - functional description (continued) rx signal sta_109 (or vocsta bit 7) 2s interrupt (it1) 75c53006.eps figure 2 st75c530 - ST75C540 14/84
v.3.12 - telephony functions st75c530/540 telephony software provides both handset and handsfree modes. st75c530/540 is connected to the phone line through a d.a.a., handset and loudspeaker are connected to st75c530/540 through amplifiers. though the d.a.a. has to comply with modem/fax regulations in most of the applications, the micro- phone and the earphone amplifier gains will be adjusted in compliance with the telephony regula- tions. the software implementedin st75c530/540 allows functions such as softclipping, agc in both modes, and full duplex mode in handsfree(see fig- ure 3). v.3.12.1 - handset mode in handset mode, all the attenuations (_spkgain, _txgain, _mikgain) are from 0db to -inf (32768 steps). agc and softclipping functions can be enabledand disabled by software (see figure 4). dual ram interface 15 adc mute dac line hybrid txa1 txa2 rxa adc 14 11 10 mic3 8 mic1 9 mic2 79 spk2 78 mute 77 spk3 76 mute 2 spk1 1 mute [0..-30]db step 3db dac att_tx coder handsfree/ handset algorithms att_mic 2 tone generator agc 2 tone detectors agc dg 75c53007.eps figure 3 : handset/handsfreemode operation v - functional description (continued) mic2 spk2_1 spk2_2 _mikgain _spkgain softclipping agc = f(i line ) rxa dp_ring txa1 txa2 _txgain agc = f(i line ) 75c53008.eps figure 4 : handset mode st75c530 - ST75C540 15/84
tx characteristics symbol parameter test conditions min. typ. max. unit gtx transmit gain _mikgain=7fff,_txgain=7fff, agc disabled v mic2 = -21dbv v mic2 = -9dbv 18 8 db db ntx transmit noise 2k w between mic2 and gnd -73 dbmp mmic microphone mute v mic2 = -21dbv 60 db vlpeak transmit softclipping level on txa1-txa2 _mikgain=7fff,_txgain=7fff, agc disabled see figure 3, v mic2 = -9dbv 2.5 vpp dtx transmit distortion _mikgain=7fff,_txgain=7fff, agc disabled see figure 3, v mic2 = -9dbv 2% rx characteristics symbol parameter test conditions min. typ. max. unit grx receive gain _spkgain=7fff , agc disabled, v rxa = -16 dbv 6 db nrx receive noise -79 dbmp mrx mute v rxa = dbv 60 db dtx receive distortion (spk2 output) _spkgain=7fff , agc disabled, v rxa = -16dbv 2 % agc the line current information is coming from the d.a.a. on dp_ring pin (frequencycoded informa- tion using by example a ts555 general purpose timer). the agc has a 6db depth . theattenuation table can be loaded to comply with each country regulation. the default table has the following val- ues. the value of the agc gain is applied to both tx and rx path (see table 1). the address of the table is given in the register @_table. the table length is 53. the agc is enabled using conf or modc command (see paragraph ovii - command set descriptiono. once the agc is running, it is possible to freeze the agc gain with the register agc_frz. softclipping the softclipping introduces a 12db gain and has a 18db depth. the softclipping value is half digital range (4000 hex) (see figure 5). v - functional description (continued) 10 4 10 3 10 2 10 v micx (mv rms ) 10 3 0 2 4 6 8 10 12 (mv rms ) d (%) vtxa1-txa2 (v rms ) distortion tx softclipping and distortion 10 2 75c53009.eps figure 5 : softclipping static gain table 1 : agc gain versus period information period (ms) <9 10 10.8 11.6 14.5 13.3 14.1 15.5 16.6 17.5 18.3 19.1 20 >20 table index <13 13 14 15 16 17 18 19 20 21 22 23 24 >24 gain (db) 0 0.7 1.5 2.2 3 3.4 4 4.5 4.8 5.1 5.4 5.6 5.8 6 st75c530 - ST75C540 16/84
v - functional description (continued) spk1p spk1n _spkgain rxa txa1 txa2 adaptive fir filter mic1 _mikgain acoustic filter adaptive attenuator nlms control nlms adaptive fir filter agc = f(i l ) _txgain softclipping agc = f(i l ) adaptive attenuator - + + - 75c53010.eps figure 6 : handsfree mode : full duplex v.3.12.2 - handsfree mode the ha ndsfree uses a mic1 and a spk1 as microphone and loudspeaker interface (see figure 6). tx characteristics symbol parameter test conditions min. typ. max. unit gtx transmit gain _mikgain=7fff,_txgain=7fff ,agc disabled, v mic1 = -21dbv 24 db ntx transmit noise 2k w between mic1 and gnd -70 dbmp mmic microphone mute v mic1 = - dbv 60 db dtx transmit distortion _mikgain=7fff,_txgain=7fff ,agc disabled, v mic1 = -9dbv 2% rx characteristics symbol parameter test conditions min. typ. max. unit grx receive gain _spkgain=7fff, agc disabled, v rxa = -33dbv 24 db mrx mute 60 db dtx receive distortion (spk1 output) _spkgain=7fff, agc disabled, v rxa = -33dbv 2 % agc the agc has the same behavior as in handset mode. furthermore, the maximum gain added by agc can be fixed by using the rx_gainmax and tx_gainmax registers. softclipping see figure 7. system stability parameter test conditions min. typ. max. unit loop attenuation in rx rxa to txa1-txa2 speaker gain is 12db, mike gain is 14db 20 db loop attenuation in tx micx to spk1p-spk1n analogique sidetone not used (see daa schematics) 20 db it is possible to add some gain switching in the tx and rx path (to reduce the gain of the loop) by using the gain_rcv and gain_xmt registers. st75c530 - ST75C540 17/84
v - functional description (continued) 10 2 10 3 vspk1 (v rms ) distortion rx softclipping and distortion 0 2 4 6 8 10 12 (mv rms ) d (%) 10 3 10 2 10 v mic2 (mv rms ) 75c53011.eps figure 7 : spk1 distortion versus rxa power spec1 power spec2 64avg 64avg 0%ovlp 0%ovlp ftop ftop 0.0 0.0 dbm rms v2 db rms vv2 -80.0 -80.0 fxd y o hz 5k line tx speaker output 75c53012.eps note : acoustic echo from speaker to microphone input with no local speech. receiving speech on line input. figure 8 : speaker and line tx power spectrums v.3.13 - low power mode sleep state can be attained by a sleepcommand. when in sleep mode, the dual port ram is unavail- able and the clocks are disabled. when entering the low power mode, the st75c530/540stops its oscillator, all the peripher- als of the dsp core are stopped in order to reduce the power consumption. the dual port ram is made inaccessible. the st75c530/540 can be awakened by a hard- ware reset, a ring signal or a dummy write at any location in the dual port ram. there is a maximum time of 20ms to restart the oscillator after waking up and an additional 5ms after the interrupt to be able to accept any com- mand coming from the host. v.3.14 - reset after a hardware reset, or an init command, the st75c530/540 clears all its internal memories, clears the whole dual port ram and starts to initial- ize the delta sigma analog converters. as soon as these initializations are completed, the st75c530/540 generates an interrupt it6 (com- mand acknoledge) and is programmed to send and receive tones, the sample clock are programmed to 9600hz. the total duration of the reset sequence is about 5ms. after that time the st75c530/540 is readyto executecommands sent by the host micro- controller. the duration of the reset signalshould be greater than 700ns. v.4 - modem interface v.4.1 - analog interface refer to block diagram on page 7. v.4.2 - general i/o and relay interface 16 pins are dedicated to the general i/o port. two are dedicated to relaydriver. the equivalent sche- matic is as follows : see figure 9. q d gio0[x] iodir0[x] iodata0[x] (write) iodata0[x] (read) q d relay[y] iorelay[y] (write) iorelay[y] (read) rgnd n 75c53013.eps figure 9 st75c530 - ST75C540 18/84
v.4.3 - crystal the crystal frequency must be 44.2368mhz for st75c530 and 49.152mhz for ST75C540 with an accuracy better that 100 ppm. when using a third harmonic crystal the schematic must be as follow : see figure 10. the crystal features are : - third harmonic, - parallel, load capacitance = 10pf, - ? 100ppm from 0 o cto70 o c, -r s <50 w , - atcut (example : sm55-10 matel). xtal h3 ** c2 27pf cog l* 0.82 m h (st75c530) 0.68 m h (ST75C540) cb 10nf c1 10pf cog ST75C540 73 72 extall xtall wire wound inductor recommanded (example : sigma-sc30) thrird harmonic (example : matel-sm55-10) * ** xtal h3 : 44.2368mhz (st75c530) 49.152mhz (ST75C540) 75c53014.eps figure 10 v.4.4 - typical application schematic the figure 11 is a block diagram designed to allow transmission of fax signals up to +0dbm and sine wave up to +6dbm on the telephone line. it allows receptionof fax signals up to 0dbm and sine waves up to +6dbm.figure12 is a blockdiagramdesigned v - functional description (continued) -1/2 600 w 1:1 line 2.2nf +8db -10db v cm txa1 txa2 rxa 75c53015.eps figure 11 -1/2 600 w 1:1 line 2.2nf 0db 0db v cm txa1 txa2 rxa 75c53016.eps figure 12 to allow transmission of modem signal up to - 10dbm and reception up to -10dbm. the opamps are +12/0v powered. with this application sche- matic the out of band transmit spectrum(from 4khz to 50khz) is below -72dbm. figures 13 and 14 are examples of application sche- maticswhich respectsgainvalue(respectivelyforfax and voice application and for modem application) andthe minimum differentialloadon txa1 andtxa2. v.4.5 - host interface the host interface is seen by the micro as a 128x8 ram, with additional registers accessible through an 8-bit address space. a selection pin (int/mot) allows to configurethe host bus for either intel or motorola type control signals. st75c530 - ST75C540 19/84
v - functional description (continued) gnd +12v 47.5k w +6v +6v 470pf 18.2k w 1% 18.2k w 1% 470nf 470nf 270pf 24k w 1% txa1 txa2 1.2k w 33k w 1% 24.3k w 1% 470nf 560 w 470nf 30k w 1% 6.21k w 1% +6v rxa 2.2nf vcm +6v +6v 22nf +6v 470nf 1:1 * * insertion loss = 2.5db between 0 and 3.4khz gnd +12v 75c53018.eps figure 14 : data mode gnd +12v 47.5k w +6v +6v 470pf 18.2k w 1% 18.2k w 1% 470nf 470nf 270pf 56.2k w 1% txa1 txa2 1.2k w 10k w 1% 24.3k w 1% 470nf 560 w 470nf 30k w 1% 6.21k w 1% +6v rxa 2.2nf vcm +6v +6v 22nf +6v 470nf 1:1 * * insertion loss = 2.5db between 0 and 3.4khz +12v gnd 75c53017.eps figure 13 : fax mode st75c530 - ST75C540 20/84
vi - user interface vi.1 - dual port ram description the dual port ram is the standard interface be- tween the host controller and the st75c530/540, for either commands or data. this memory is ad- dressed through a 7-bit address bus. the locations from $00 to $3f are ram location, while locations from $40 to $60 are control registers dedicated to the interrupt handling and the general io port and relay output. severalfunctionalareas are defined in the dual port ram mapping : - the command area, - the report area, - the status area, - the optional status area, - the data buffer area, - the interrupt control area, - the general i/o and relay output area. vi.1.1 - mapping vi.1.1.1 - command area the command area is located from $00 to $04. address $00 holds the command byte comsys, and the next four locations hold the parameters compar[0..3].the command parametersmust be entered before the command word is issued. once the command has been entered,the command byte is reset and an acknowledge report is issued. anew command should not be issued before the acknow- ledge counter comack is incremented. vi.1.1.2 - report area the report area is located from address $05 to address $07. location $05 holds the acknowledge counter comack. each time a command is ac- knowledged, the report bytes comrep[0..1] (if any) are written by the st75c530/540 into loca- tions $06 and $07, and the content of comack is incremented. this counter allows the st75c530/540 to accurately monitor the com- mand processing. vi.1.1.3 - status area the statusarea is located from address$08 to $0b. the errorstatusword syserrislocatedat address $08. this error status word is updated each time an error condition occurs. an optional interruption it0 may additionallybe triggered in the case of an error condition. locations $09 and $0a hold the general status bytes status[0..1]. the meaning of the bits dependson the mode of operation,and is described in chapter viii. the third byte at address $0b holds the quality monitor byte staqua. vi.1.1.4 - optional status area the user can program (through the dosr com- mand) the four locations staopt[0..3] of the op- tional status area ($0c to $0f) for the real time monitoring of four arbitrary memory locations. vi.1.1.5 - data buffer area the data area is made of four 8-byte buffers (see paragraph vi.1.3 ahost interface summaryo). two are dedicated to transmission and the two others to reception. each of the four buffers is attached to a status byte. the meaningof the status byte depends on the selected format of transmis- sion. within each buffer, d0 represents the first bit in time. vi.1.1.6 - vocoder buffer area (vocoder mode) this area is made of a 18+2 byte buffer. this buffer contains the vocoder frame. the first 18 bytes vocdata contain the coded frame and the other 2 bytes voccorr the error corrections bit (only valid in low bit rate mode). in the receive mode (coder) the st75c530/540 codes the received samples and writes the corres- ponding bytes in the buffer. if the low bit rate mode is selected, the st75c530/540computes the error corrections 2 bytes and writes them in the buffer. in the transmit mode (decoder) the st75c530/540reads the 18 coded bytes decodes them and sends the signal to the analog output. in the low bit rate mode if the error correction is enabled, prior the decoding, the st75c530/540 reads the 2 error correction bytes and, if any, corrects the first 18 bytes. a mechanism of flags to share the buffer access between the st75c530/540and the hostcontroller is controlled by the vocsta byte : - in coder mode, when the st75c530/540 has finis-hed writing the vocdata and voccorr bytes, it writes $14 in vocsta and generate an interrupt it1. the host must read the data buffer then clear the vocsta byte. - in decoder mode, the host must feed the vocdata and, optionaly,the voccorr bytes, then write $14 (if low bit rate) or $12 (if adpcm) in vocsta. the st75c530/540 will read the vocdata and voccorr bytes, clear the vocsta and generate an interrupt it1. a si- lence frame can be generated, in either low bit rate or adpcm mode, by writing 00 in all the vocdata buffer, including the error correction bytes voccorr. st75c530 - ST75C540 21/84
vi.1.1.7 - interrupt control area the interrupt area, that start after the address $40 controls the behaviour of the interrupts mecha- nism. register itsrcr defines the source of the interrupt, the register itmask allows independent enabling or disabling of any of the interrupt's source, registers itrest0 to itrest6 reset the corresponding interrupt source. theseregistersare not affectedby a initcommand, they are only reseted by a hardware reset signal. vi.1.1.8 - general io and relay output area a set of 5 registers is directly accessible by the controller to program the general io pins and relay outputs (see paragraph vi.1.3 ahost inter- face summaryo). two registers iodir0 and io- dir1 define the type of the io pin, either input or output (0 = input, 1 = output), and two registers iodata0 and iodata1 define the io pin signals. the fifth register defines the relay output signals. theseregistersare not affectedby a initcommand, they are only reseted by a hardware reset signal. the general io are setup as input after the power up or an hardware reset. the relay output are open after power up or an hardware reset. vi.1.2 - interruptions the st75c530/540 can generate 7 interrupts for the controller. the interrupt handling is made with a set of registers located from $40 to $5f. the interruptions generated by the st75c530/540 come from several sources. once the st75c530/540raises an interrupt, a signal (sintr) is sent to the controller. the controller has then to processthe interruptandclearit. theinterruptsource can be examined in the interrupt source register itsrcr located a $50. according to the itsrcr bits, the interrupt source can be determined. then writing a zero at one of the memory location $40 to $46 (reset interrupt register itres[0..6]) will re- set the corresponding interrupt (and thus acknow- ledge it). the source of the interrupt can be masked globally or individually using the interrupt mast register itmask located at $4f. the interrupt sources are : - it0 : error this signifies that an error has occurred and the error code is available in the error status byte syserr. this byte can be selectively cleared by the cse command. - it1 : vocoder buffer each time the st75c530/540 have coded a frame (coder mode) or decoded a frame (de- coder mode) this interrupt is generated. - it2 : tx buffer each time the st75530/c540frees a data buffer, this interrupt is generated. - it3 : rx buffer each time the st75c530/540 has filled a data buffer, this interrupt is generated. - it4 : status byte this signifies that the status byte has changed and must be checked by the controller. - it5 : low power mode the st75c530/540has been awakened from the low power mode by a low level on the ring pin or a dummy write issued by the host. - it6 : command acknowledge this signifies that the st75c530/540 has read the last command entered by the host, incre- mented the command counter comack, and is ready for a new command. note : interrupt registers are cleared after a hard- ware reset. these registers are not affected by a init command. vi - user interface (continued) st75c530 - ST75C540 22/84
sintr (open drain) 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 r s q it6 : command itrest 6 (write only) itsrcr (read only) itmask (read write) r s q it5 : low power itrest 5 (write only) r s q it4 : status itrest 4 (write only) r s q it3 : rx buffer itrest 3 (write only) r s q it2 : tx buffer itrest 2 (write only) r s q it1 : vocoder buffer itrest 1 (write only) r s q it0 : error itrest 0 (write only) 75c53019.eps figure 15 : functional schematic vi - user interface (continued) st75c530 - ST75C540 23/84
vi.1.3 - host interface summary address (hex) description size (byte) mnemonic command area $00 command 1 comsys $01-$04 command parameters 4 compar[0..3] report area $05 acknowledge counter 1 comack $06-$07 report 2 comrep[0..1] status area $08 error status 1 syserr $09-$0a general status 2 status[0..1] $0b quality monitor 1 staqua $0c-$0f optional report 3 staopt[0..3] data buffer area (fax modes and data modes) $1c data rx buffer 0 status 1 dtrbs0 $1d-$24 data rx buffer 0 8 dtrbf0[0..7] $25 data rx buffer 1 status 1 dtrbs1 $26-$2d data rx buffer 1 8 dtrbf1[0..7] $2e data tx buffer 0 status 1 dttbs0 $2f-$36 data tx buffer 0 8 dttbf0[0..7] $37 data tx buffer 1 status 1 dttbs1 $38-$3f data tx buffer 1 8 dttbf1[0..7] vocoder buffer area (vocoder mode) $1c vocoder buffer status 1 vocsta $1d-$2e vocoder buffer data 18 vocdata $2f-$30 vocoder buffer corrector 2 voccorr interrupt area $40-$46 reset interrupt register 7 itrest[0..6] $4f interrupt mask register 1 itmask $50 interrupt source register 1 itsrcr general io and relay $60 i/o direction 0 1 iodir0 $61 i/o direction 1 1 iodir1 $62 i/o data 0 1 iodata0 $63 i/o data 1 1 iodata1 $64 i/o relay register 1 iorelay note : registers which address is higher or equal to $40 are not affected by a init command or a low power wake-up. they are reseted only by a hardware reset. vi - user interface (continued) st75c530 - ST75C540 24/84
vi.2 - command set the command set has the following attractive features : - user friendly with easy to remember mnemonics, - possibility of straightforward expansion with new commands to suit specific customer require- ments, - easy upgrade of existing software using previous modem based sgs-thomson products. the command set has been designedto providethe necessaryfunctionalcontrolon the st75c530/540. each command is classified according to its syntax and the presence/absence of parameters. in the case of a parametric command, parameters must first be written into the dual port ram before the command is issued. acknowledge and error report is issued for each command entered. vi.2.1 - command set summary vi.2.1.1 - operational control commands init initialize. initialize the modem engine. set all parameters to their default values and wait for commands of the control processor. non parametric command. idt identify. return the product identification code. non parametric command. sleep turn to low power mode, the st75c530/540 enters the low power mode and stops its crystal oscillator to reduce power consumption. in this mode all the clocks are stopped and the dual ram is unreachable. hshk handshake. begins the handshake sequence.the modem engine generates all the sequences defined in the itu-t recommendations. a status report indicatesto the controlprocessorthe state of the handshake. this command only applies to modes where a handshake sequence is defined. a conf command must have been issued prior to the use of hshk. non parametric command. stop fax stop. stop fax half-duplex transmitter. non parametric command. rtra retrain. begin a retrain sequence in v.32bis/v.32 or v.22bis modes as described in the itu-t recommendations (ST75C540 only). sync fax synchronize. start/stopof faxhalf- duplex receiver. parametric command. cse clearstatuserror.selectivelyclearstheerror statusbytesyserr. parametric command. setgn set gain. this command sets the global gain factor, which is used for the transmit samples. parametric command. vi.2.1.2 - data communication commands xmit transmit data. start/stop the transmission of data. after a xmit command, the st75c530/540sends the data contained in its dual port ram. form selects the transmission format. this command configures the data interface for both receiver and transmitter according to the selected data format. parametric command (hdlc, uart or synchronous). vi.2.1.3 - memory handling commands mwi mwlo mw memory write indirect memory write low word memory write. this command is used to write an arbitrary 16-bit value into the writable memory location currently specified by a parameter. parametric command. mri mrlo mr memory read indirect memory read low word memoryread. this command allows the controller to read any of the eram or crom (st75c530/540 memory spaces) location without interrupting the processor. parametric command. cr complex read. this command allows the controller to read at the same time the real and imaginary part of a complex valuestoredinadoubleeramor crom location. this feature is very interesting for eye pattern software control and for equalization monitoring. this command insures that the real and imaginary pa rts are sampled in the memory at the same time (integrity). parametric command. vi - user interface (continued) st75c530 - ST75C540 25/84
vi.2.1.4 - configuration control commands asel select the analog path option, like microphone input, speaker attenuation. parametric command. conf configure. this command configures the modem engine for data transmission and handshake procedures (if any) in any of the supported modes. the transmission parameters are set to their default values and can be modified with the modc command. parametric command. modc modify configuration. this command allows modification of some of the parameters which have been set up by the conf command. it can also be used to alter the mode of operations (short train). parametric command. dosr define optional status report. this command allows the modification of the optional status report located in the status area of the dual port ram. one can thus select a particular parameter to be monitored during all modes of operation. parametric command. dsit define status interrupt. this command allows the programming of the status word bit that will generate an interrupt to the controller. parametric command. vi.2.1.5 - tone generation commands tone selecttone. programsthe tone generator(s) for the desired default tone(s). additional mnemonics provide quick programming of dtmf tones or other currently used tones. parametric command. deft define tone. programs the tone generator(s) for arbitrary tone synthesis. parametric command. tgen tone generator control. enables or disables the tone generator(s). parametric command. vi.2.1.6 - tone detection commands tdrc read tone detector coefficient. read one tone detector coefficient. parametric command. tdwc write tone detector coefficient. write one tone detector coefficient. parametric command. tdrw read tone detector wiring. read one tone detector wiring connection. parametric command. tdww write tone detector wiring. write one tone detector wiring connection. parametric command. tdz clear tone detector cell. clear internal variables of a tone detector cell. parametric command. vi.2.1.7 - miscellaneous commands call call a subroutine. call a subroutine with one parameter. parametric command. jsr call a low level subroutine. call an internal subroutine with one parameter. parametric command. vi.3 - command set short form cci command mnemonic value description xmit 0x01 transmit data setgn 0x02 set transmit gain sleep 0x03 power down the st75c530/540 hshk 0x04 fax start transmitter rtra* 0x05 retrain (v.32bis/v.32 and v.22bis) init 0x06 initialize (software reset) cse 0x08 clear error status word form 0x09 define data format dosr 0x0a define optional status report asel 0x0b select the analog path options tone 0x0c generate predefined tones tgen 0x0d enable tone generator deft 0x0e define arbitrary tone mr 0x10 memory read cr 0x11 complex read mw 0x12 memory write dsit 0x13 define status interrupt idt 0x14 return product identification code jsr 0x18 call a low level routine call 0x19 call a routine tdrc 0x1a tone detector read coefficient tdrw 0x1b tone detector read wiring tdwc 0x1c tone detector write coefficient tdww 0x1d tone detector write wiring tdz 0x1e tone detector clear cell conf 0x20 configure modc 0x21 modify default configuration stop 0x25 fax stop transmitter sync 0x26 fax synchronize receiver mri 0x28 memory read indirect mrlo 0x29 memory read low word mwi 0x2a memory write indirect mwlo 0x2b memory write low word * ST75C540 only. vi - user interface (continued) st75c530 - ST75C540 26/84
vi.4 - status - reports vi.4.1 - status the st75c530/540 has a dedicated status report- ing area located in its dual port ram. this allow a continuous monitoring of the status variables with- out interrupting the st75c530/540. the first status byte gives the error status. issuing of an error status can also be flagged by a mask- able interrupt for the controller. the signification of the error codes are given in chapter viii. the second and third status bytes give the general status of the modem. these status include for example the itu-t circuit status and other items described in chapter viii astatus descrip- tiono. these two status can generate, when a change occurs, an interrupt to the controller ; each bit of the two byte word can be masked inde- pendently. the forth byte gives in real time a measure of the receptionquality. thisinformationmay be used by the controller to monitor the quality of the received bits. four other locations are dedicated for custom status reporting. the controller can program the st75c530/540 for a real time monitoring of any of its internal ram location. high byte or low byte of any word can thus be monitored. vi.4.2 - reports the st75c530/540 features an acknowledge and report facility. the acknowledge of a command is monitored by a counter comack located in the dual port ram. each time a command is read from the command area, the st75c530/540 will incre- ment this counter. for instance, when a mr (mem- ory read) command is issued, the data is first written in the report area, and the counter is incre- mented afterwards. this way of processinginsures data integrity and gives additional synchronization between the controller and the data pump. vi.5 - data exchanges the st75c530/540 accepts many kinds of data exchange: the defaultmode uses the synchronous parallel exchange. other modes include hdlc framing support and uart. detailed description of the data buffer exchanges modes is available in the paragraph x. vi.5.1 - synchronous parallel mode the data exchanges are made through the dual port ram and are byte synchronous oriented. the double buffer facilities of the st75c530/540 allow an efficient buffering of the data. vi.5.1.1 - transmit the controller must first fill at least the first buffer of data (tx buffer 0) with the bits to be transmitted. in order to perform this operation, the controller must first check the tx buffer 0 status word dttbs0. if this buffer is empty, the controller fills the data buffer locations (up to 64 bits), and then writes in dttbs0 the number of bytes contained in the buffer. the controller can then either proceed with the second buffer or initiate the transmission with a xmit command. the st75c530/540copies the contentsof the data buffer and then clears the buffer status word in order to make it again available, then generates an it2 interrupt. the number of bytes specified by the status word is then queued for transmission. the process goes on with the two buffers until an xmit command stops the transmission. after the finish- ing xmit command has been issued, the last buff- ers are emptied by the st75c530/540. errors occur when both buffersare empty while the transmit bit queue is also empty. error is signalled with an it0 interruption to the controller. vi.5.1.2 - receive the controller should take care of releasing the rx buffers before the data carrier detect goes true. this is made by writing zero in the rx buffer status 0 and 1. the st75c530/540 then fills the first buffer, and once filled sets the status word with the number of bytes received and then generates an it3 interrupt. it then takes control of the second buffer and operates the same way. the controller must check the status of the buffers and empty them. once the data read, the controller must release the used buffer and wait for the next buffer to be filled. error occurs when both buffers are declared full, and incoming bits continue to arrive from the line. error is signaled by an it0 interrupt. vi.5.2 - hdlc parallel mode this mode implements part of the high level data link control formats and procedures. it is well suited for error correcting protocols like ecm or faxt4/t30 recommendations.it supportsthe flag- ging generation,16-bit frame check sequence,as well as the zero insertion/deletion mechanism. vi.5.3 - uart parallel mode this mode implement a 7 or 8 bit data format, it is well suited for caller id or minitel applications. vi - user interface (continued) st75c530 - ST75C540 27/84
vii - command set description commands are presented according to the following form : command command name meaning command opcode hexadecimal digit xxxxxxxx synopsis short description of the functions performed by the command. parameters field byte pos. value definition name x b..a xx * explanation of the parameter default value field name of the addressed bit field. byte index (or address in the dual port ram) of the parameter byte (from 1 to 4). pos. bit field position inside the parameter byte. can either be a single position (from 0 to 7, 0 being lsb) or a range. value possiblevaluesfor thebit(resp. bitfield). range meansall valuesare allowed.a starmeansa default value. valuesare expressed either under the form of a bit string, or under hexadecimal format. asel asel opcode: 0b 00001011 synopsis select the analog path options. this command select the attenuation/mute of the outputs txa1/txa2 and spk1/spk2/spk3. this command select also the source of the mic signal mic1/mic2/mic2 and the source of the line signal rxa/mic3. parameters field byte pos. value definition asel_aspk1 1 7..4 0000* 0001 0010 ... 1010 1011 other infinity attenuation 30db attenuation 27db attenuation ... 3db attenuation 0db attenuation reserved asel_micsel 2 1..0 00* 01 10 11 select rx input as mic1 select rx input as mic1 select rx input as mic2 select rx input as mic3 asel_linesel 2 2 0* 1 select rxa as line input select mic3 as line input asel_espk1 2 3 0* 1 spk1 output muted spk1 output normal asel_espk2 2 4 0* 1 spk2 output muted spk2 output normal asel_espk3 2 5 0* 1 spk3 output muted spk3 output normal asel_mtxa 2 7 0* 1 txa output normal txa output muted call call a subroutine call opcode: 19 00011001 synopsis call allows to execute a part of the st75c530/540 firmware with a specific argument. parameters field byte pos. value definition c_addr_l 1 7..0 low byte of the call address c_addr_h 2 7..0 high byte of the call address c_data_l 3 7..0 low byte of the argument c_data_h 4 7..0 high byte of the argument this instruction can be used with sgs-thomson microelectronics application laboratory support for special applications development or debugging needs. contact your local representative. st75c530 - ST75C540 28/84
conf configure for operations conf opcode : 20 00100000 synopsis conf allows the complete definition of the st75c530/540 operation, including the mode of operation (tone, fax transmit, voice transmit, voice receive, dtmf receiver, ...) and the modem or vocoder parameters (standard, speed, ...). according with the 4 first bits of the conf parameter the st75c530/540 is put into the following mode of operation. conf_ oper mode detectors tone (2) tone (3) dtmf ring vad v.21 flag cpt (5) answ (6) 0000* 0001 0010 0100 1000 1001 1100 1111 other tone tonecid(1) decoder transparent coder room-monitor handset/handsfree modem reserved 16 6 0 6 0 0 0 0 4 4 4 4 4 4 2 4 (7) yes yes yes yes yes yes no yes (4) yes yes yes no yes no no no no no no no yes no no no yes yes no no no no no yes yes yes no yes no no no yes (4) yes no no yes no no no no notes : 1. this mode includes v.23/bell202 fsk demodulator and uart. 2. this primary tone detectors allows detection of signal up to 3.3khz. (sampling rate 7.2khz). 3. thissecondary tone detectors allowsdetectionof signalupto1.8khz (withsamplingrate4.8khz) or upto3.3khz (withsampling rate9.6khz). 4. the dtmf detector and call progress tone detector (cpt) are available only for v.21 channel 2. 5. sta_cpt0, sta_cpt1 and sta_cpt10 in status0. 6. sta_ccitt and sta_at in status1. 7. not available in v.32bis/v.32. vii - command set description (continued) st75c530 - ST75C540 29/84
parameters when the conf_oper is set to f, selecting the modem mode of operation,the parameters have the following meaning : field byte pos. value definition conf_oper 1 3..0 1111 select modem mode conf_anal 1 4 0 1 normal mode analog loop back (test mode only) conf_pstn 1 5 0 1 pstn (carrier detect set to -43/-48dbm) leased line (carrier detect -33/-38dbm) conf_ao 1 6 0 1 answer mode originate mode conf_dtinit (only in tone mode) 170 1 global init of secondary tone detector partial init of secondary tone detector (8) conf_mode 2 5..0 0 1 2 3 4 5 6 7 8 9 a b c d other automode (v.32bis/v.32/v.22bis/v.22) (9) bell 103 (full duplex) bell 212a (full duplex) (9) v.21 (full duplex) v.23 (full duplex) v.22 (full duplex) (9) v.22bis (full duplex) (9) v.27ter v.29 v.17 v.32 (full duplex) (9) v.32bis (full duplex) (9) v.33 (half duplex) v.21 channel 2 reserved conf_txeq 2 7..6 0 1 2 3 no transmit equalizer transmit equalizer #1 transmit equalizer #2 transmit equalizer #3 (v.17/v.33/v.29/v.27ter) conf_car 3 0 0 1 1800hz carrier (v.17/v.33 only) 1700hz carrier (v.17/v.33 only) conf_tcm 3 1 0 1 treillis coding not allowed (v.32 only) treillis coding allowed (v.32bis, v.32) conf_sp0 3 7..4 xxx1 xx1x x1xx 1xxx 1200bps allowed (v.22, v.22bis) (10) 2400bps allowed (v.22bis, v.27) (10) 4800bps allowed (v.32bis, v.32, v.27, v.29) (10) 7200bps allowed (v.32bis, v.29, v.17) (10) conf_sp1 4 2..0 xx1 x1x 1xx 9600bps allowed (v.32bis, v.32, v.29, v.17) (10) 12000bps allowed (v.32bis, v.17, v.33) (10) 14400bps allowed (v.32bis, v.17, v.33) (10) notes : 8. with conf 80 00 00 00 the coefficients of secondary tone detectors are not initialized. 9. ST75C540 only. 10. v.22bis, v.22, v.32bis and v.32 modes ST75C540 only. vii - command set description (continued) st75c530 - ST75C540 30/84
parameters coder and decoder modes in the vocoder modes, either coder or decoder, (conf_oper equals 2 or 8) the parameters have the following meaning : field byte pos. value definition conf_oper 1 3..0 - define mode : see table above conf_code 3 0 0 1 low bit rate coded adpcm coded conf_vpf 3 1 0 1 decoder post filter off decoder post filter on (not in adpcm) conf_vasp 3 3..2 00 01 10 11 adpcm 32000 bps adpcm 24000 bps adpcm 16000 bps reserved conf_ec 3 4 0 1 line echo canceller disabled line echo canceller enabled conf_src 3 5 0 1 coder source is line input coder source is audio input conf_supsil 3 6 0 1 coder silence supressor disabled coder silence supressor enabled conf_ercor 3 7 0 1 low bit rate decoder disable error correction low bit rate decoder enable error correction parameters room-monitor mode in the room monitor mode (conf_oper equals 9) the parameters have the following meaning : field byte pos. value definition conf_oper 1 3..0 1001 define room-monitor mode conf_ec 3 4 0 1 line echo canceller disabled line echo canceller enabled parameters handset/handsfree mode in the handset/handsfree mode (conf_oper equals c), the parameters have the following meaning : field byte pos. value definition conf_oper 1 3..0 1100 define handset/handsfree mode conf_inhini 3 6 0 1 init all telephony parameters disable init of telephony parameters conf_hfree 3 7 0 1 handset mode handsfree mode conf_lec 4 0 0 1 line echo canceller enabled line echo canceller disabled conf_aec 4 1 0 1 audio echo canceller enabled audio echo canceller disabled conf_fulld 4 2 0 1 full duplex mode enabled half duplex mode enabled conf_softrx 4 3 0 1 softclipping enabled on rx softclipping disabled on tx conf_agc 4 4 0 1 agc active agc frozen conf_softtx 4 5 0 1 softclipping enabled on tx softclipping disabled on rx vii - command set description (continued) st75c530 - ST75C540 31/84
cr complex read cr opcode: 11 00010001 synopsis cr allows the reading of a complex parameter.the parameterspecifiesthe parameter address(for the real part : the imaginary part is next location). cr returns the high byte value of both real and imaginary part of the addressed complex parameter(see chapterviii astatus descriptiono). parameters field byte pos. value definition cr_addr_l 1 7..0 low byte of the 16-bit address cr_addr_h 2 7..0 high byte of the 16-bit address cse clear error status cse opcode: 08 00001000 synopsis cse is used to clear the st75c530/540 error status syserr byte. it is also used as an acknowledge to the error condition handler. parameters field byte pos. value definition err_mask 1 7..0 error mask. see report appendix for detailed meaning deft define arbitrary tone deft opcode: 0e 00001110 synopsis deft programs one of the four tone generator for arbitrary tone generation.the parameter is the frequency of the generated tone expressed in hertz between 0 and 3600hz. parameters field byte pos. value definition tone_gen_sl 1 1..0 index of the tone generator (3..0) tone_freq_l 2 7..0 low byte of the frequency tone_freq_h 3 7..0 high byte of the frequency (internally masked with 0f) tone_scale 4 7..0 amplitude scaling factor (high byte) 3f gives the nominal amplitude dosr define optional status report dosr opcode: 0a 00001010 synopsis dosr specifies the address of the ram variables to be monitored in the 4 locations staopt[0..3] of the dual port ram. it also specifies the assignment within the 4 locations. parameters field byte pos. value definition sta_opt_ass 1 1..0 0..3 index of the staopt destination sta_opt_adl 2 7..0 low byte of source address sta_opt_adh 3 3..0 high byte of source address sta_opt_hl 3 7 0 1 select low byte of source select high byte of source vii - command set description (continued) st75c530 - ST75C540 32/84
dsit define status interrupt dsit opcode: 13 00010011 synopsis dsit specifies the bit mask used with the status[0] and status[1] byte to generate an interrupt it4 to controller. each time a bit change happens in the status words, assuming the corresponding bit mask will be set, an interrupt will be generated. parameters field byte pos. value definition sta_it_msk0 1 7..0 status[0] bit mask pattern sta_it_msk1 2 7..0 status[1] bit mask pattern note : the default it status is 0x3f for status[0]and 0xff for status[1]. form select transmission format form opcode: 09 00001001 synopsis form defines the type of transmission used on the line. parameters field byte pos. value definition x_sync 1 2..0 000* 001 010 011 100 synchronous format transmit continous a1o (1) hdlc framing transmit continous o0o (1) uart x_anbit 2 1..0 00 01 7 bit per character 8 bit per character x_apar 2 3..2 00 01 10 no parity even parity odd parity x_astop 2 5 0 1 1 stop bit (1) 2 stop bit (1) note : 1. valid only when transmitting. hshk handshake hshk opcode: 04 00000100 synopsis hshk is used to command the st75c530/540 to begin the transmit handshake sequence processing. the progress of the handshake is reported to the control processor. parameter non parametric command. vii - command set description (continued) st75c530 - ST75C540 33/84
idt identify idt opcode: 14 00010100 synopsis idt returnthest75c530/540hardwareandsoftwarereleasenumber.seeparagraphviii.1.4. parameter non parametric command. init initialization init opcode: 06 00000110 synopsis init forces the st75c530/540 to reset all parameters to their default conditions and restart operations. parameter non parametric command. note : this command makes a software reset of the st75c530/540 and so cannot have the regular handshake protocol. it does not increment the comack, neither generate an interrupt. jsr call a low level subroutine jsr opcode: 18 00011000 synopsis jsr allows to execute a part of the st75c530/540 firmware with a specific argument. parameters field byte pos. value definition c_addr_l 1 7..0 low byte of the call address c_addr_h 2 7..0 high byte of the call address c_data_l 3 7..0 low byte of the argument c_data_h 4 7..0 high byte of the argument this instruction can be used with sgs-thomson microelectronics application laboratory support for special applications development or debugging needs. contact your local representative. vii - command set description (continued) st75c530 - ST75C540 34/84
modc modify configuration modc opcode: 21 00100001 synopsis modc allows the modification of the parameters defined by the conf command. parameters field byte pos. value definition modc_sdm 1 0 0 1 normal data mode short data mode (e.g. tvr) (5) modc_dv21f 1 1 0 1 normal v.21ch2 (1) disable v.21ch2 flag detector modc_ddtmf 1 2 0 1 normal dtmf detector (1) disable dtmf detector modc_dtdt4 1 3 0 1 normal secondary tone detector (1) disable secondary tone detector modc_dtdt16 1 4 0 1 normal primary tone detector (1) disable primary tone detector modc_sh 1 6 0* 1 normal training sequence short training sequence (2) modc_fs 1 7 0* 1 secondary tone detector sampling frequency is 4.8khz secondary tone detector sampling frequency is 9.6khz modc_v22g (6) 2 1..0 00* 01 10 no guard tone 1800hz guard tone (v.22bis/v.22) 550hz guard tone (v.22bis/v.22) modc_fpt 2 3..2 00* 01 10 no echo protection tone long echo protection tone (180ms) (4) short echo protection tone (30ms) (4) modc_nota (6) 240* 1 answer mode : generate answer tone for handshake originate mode : wait answer tone for handshake answer mode : do not generate answer originate mode : do not wait answer tone modc_nosa (6) 260* 1 cut answer tone when receiving aa (v.32bis, v.32) continue answer tone when receiving aa. modc_noqa (6) 270* 1 enable v.32bis/v.32 autoretrain on quality. disable v.32bis/v.32 autoretrain on quality. modc_adcfd 3 0..3 0000* 0001 0010 0011 1111 1110 1101 0111 other low bit rate decoder voice frame duration 30ms (nominal) low bit rate decoder voice frame duration 35ms (+16%) low bit rate decoder voice frame duration 40ms (+33%) low bit rate decoder voice frame duration 45ms (+50%) low bit rate decoder voice frame duration 25ms (-16%) low bit rate decoder voice frame duration 20ms (-33%) low bit rate decoder voice frame duration 15ms (-50%) low bit rate decoder pause reserved modc_cod 3 5 0 1 low bit rate coder disabled low bit rate coder enabled (3) modc_lec 4 0 0 1 line echo canceller enabled line echo canceller disabled modc_aec 4 1 0 1 audio echo canceller enabled audio echo canceller disabled (3) modc_fulld 4 2 0 1 full duplex mode enabled half duplex mode enabled modc_softrx 4 3 0 1 softclipping enabled on rx softclipping disabled on rx modc_agc 4 4 0 1 agc active agc frozen modc_softtx 4 5 0 1 softclipping enabled on tx softclipping disabled on tx notes : 1. in the modes where they are active. 2. short train sequence must be preceded by at least one successful long train sequence at the same data rate. for v.17 a successful long train at any data rate must preceded the short train. 3. only coder or decoder can be enabled at the same time. 4. only when sending v.17, v.33, v.29 or v.27ter. 5. french minitel application (tvr : teletel vitesse rapide). 6. ST75C540 only vii - command set description (continued) st75c530 - ST75C540 35/84
mr memory read mr opcode: 10 00010000 synopsis mr allowsthe readingof a 16-bitparameter.the parameterspecifiesthe parameteraddress. parameters field byte pos. value definition mr_addr_l 1 7..0 low byte of the 16-bit address mr_addr_h 2 7..0 high byte of the 16-bit address mri memory read indirect mri opcode: 28 00101000 synopsis mri allows the reading of a 16-bit parameter. the parameter specifies an indirect address. refer to the aram mapping application noteo (delivered on request according to revision number). the advantage to use mri instead of mr is that the indirect address is constant over the different release of the product. parameters field byte pos. value definition mri_iaddr 1 7..0 indirect address mrlo memory read low word mrlo opcode: 29 00101001 synopsis mrlo allows the reading of the memory location which address coresponds to the previous mr or mri absolute adress minus 1. this command must be preceded by a mr or mri command. this command does not have any parameter. the double word reading is executed by the mr or mri previous command. mw memory write mw opcode: 12 00010010 synopsis mw allows the writing of a 16-bit parameter. the parameter specifies the address as well as the value to be transferred. parameters field byte pos. value definition mw_addr_l 1 7..0 low byte of the 16-bit address mw_addr_h 2 7..0 high byte of the 16-bit address mw_value_l 3 7..0 low byte of the 16-bit value mw_value_h 4 7..0 high byte of the 16-bit value vii - command set description (continued) st75c530 - ST75C540 36/84
mwi memory write indirect mwi opcode: 2a 00101010 synopsis mwi allows the writing of a 16-bit parameter. theparameters specifies an indirect address as well as the value to be transferred.refer to the aram mapping applicationnoteo (delivered on request accordingtorevisionnumber).theadvantagetousemwiinsteadofmwisthattheindirectaddress is constant over the differentrelease of the product. parameters field byte pos. value definition mwi_iaddr 1 7..0 indirect address mwi_ivalue_l 2 7..0 low byte of the 16-bit value mwi_ivalue_h 3 7..0 high byte of the 16-bit value mwlo memory write low word mwlo opcode: 2b 00101011 synopsis mwlo allows the writing of a 16-bit parameter at the address defined by the following mw or mw absolute address minus 1. this command must be followed by a mw or mwi command.the double word writing is executed by the mw or mwi following command. parameters field byte pos. value definition mwlo_value_l 1 7..0 low byte of the 16-bit value mwlo_value_h 2 7..0 high byte of the 16-bit value rtra (ST75C540 only) retrain rtra opcode: 02a 00000101 synopsis rtrais used to force the st75c530/540 to initiate a retrain sequence or a rate negotiation. if modc_noqua bit is set, the st75c530/540 will initiate a transmission at the maximum speed defined by the rtra parameter, otherwise it will found the best reliable speed based on the quality of the line (within the rtra allowed speed). parameters field byte pos. value definition rtra_neg0 1 0 0 1 retrain (v.22bis, v.32, v.32bis) ratr negotiation (v.32bis, v.22bis) rtra_sp0 1 7..4 xxx1 xx1x x1xx 1xxx 1200bps allowed (v.22bis) 2400bps allowed (v.22bis) 4800bps allowed (v.32bis, v.32) 7200bps allowed (v.32bis) rtra_sp1 2 2..0 xx1 x1x 1xx 9600bps allowed (v.32bis, v.32) 12000bps allowed (v.32bis) 14400bps allowed (v.32bis) vii - command set description (continued) st75c530 - ST75C540 37/84
setgn set output gain setgn opcode: 02 00000010 synopsis setgn is a command which sets the scaling factor of the transmit samples. it is used for setting the output level or for setting the level of the tone generators. the gain value is given in the form of a 2's complement 16-bit value. parameter field byte pos. value definition gain_l 1 7..0 range ff* low byte of the 16-bit gain value gain_h 2 7..0 range 7f* high byte of the 16-bit gain value example gain (db) gain (hex) gain (db) gain (hex) gain (db) gain (hex) 0 7fff -5 47fa -10 287a -1 7214 -6 4026 -11 2413 -2 65ac -7 392c -12 2026 -3 5a9d -8 32f5 -13 1ca7 -4 50c3 -9 2d6a -14 198a the multiplication factor is : 10 (-1/20) = 0.89125 for 1db step. sleep turn to sleep mode sleep opcode: 03 00000011 synopsis sleep is used to force the st75c530/540 to turn to low power mode. parameter non parametric command. note : when receiving this command the st75c530/540 will stop processing and so cannot have the regular handshake protocol. it does not increment the comack, neither generate an interrupt. stop fax stop transmitter stop opcode: 25 00100101 synopsis stop is used, in fax modes, to force the st75c530/540 to turn off the transmitter in accordance with the corresponding itu-t v.33/v.17/v.29/v.27recommendation. parameter non parametric command. note : when receiving this command the st75c530/540 will stop sending regular data. this command must be preceded by a xmit stop command. the st75c530/540 will wait until all the transmit buffers are sent before starting the stop sequence. sync fax synchronize the receiver sync opcode: 26 00100110 synopsis sync is used, in fax modes, to force the st75c530/540 to start/stop the receiver in accordance with the corresponding itu-t v.33/v.17/v.29/v.27recommendation.as soon as the st75c530/540 receives the sync start command it sets its receiver to detect the fax synchronization signal.this command is the equivalent hshk command for the receiver. parameters field byte pos. value definition rx_sync 1 0 0* 1 stop receiver start receiver synchronization vii - command set description (continued) st75c530 - ST75C540 38/84
tdrc tone detector read coefficient tdrc opcode: 1a 00011010 synopsis tdrc read one coefficient of the selected tone detector cell. parameters field byte pos. value definition td_cell 1 4..0 0..13 tone detector cell number td_c_addr 2 7..0 0..b 10 20 30 (1) 40 (1) biquad coefficient energy coefficient static level energy coefficient for relative comparison gain for relative comparison the command answer is : low byte of coefficient followed by high byte of coefficient. note 1 : value 30 and 40 of byte 2 are available only for secondary tone detector. tdrw tone detector read wiring tdrw opcode: 1b 00011011 synopsis tdrw read wiring of the selected tone detector cell. parameters field byte pos. value definition td_cell 1 4..0 0..13 tone detector cell number for primary tone detector td_w_addr 2 0 0 1 other biquad and energy input comparator inputs reserved the command answer is : a) if td_w_addr = 0 : - first byte is the node number of the signal connected to biquadratic filter input. - second byte is the node number of the signal connected to the energy estimator input. b) if td_w_addr = 1 : - first byte is the node number of the signal connected to comparator negative input. - second byte is the node number of the signal connectedto the comparator positive input. for secondary tone detector td_w_addr is not defined. - first byte is 00 if relative comparison is not mandatory, first byte is 01 if relative comparison is mandatory. - second byte is for the configuration of the secondary tone detector : c0 configuration 1+1 of secondary tone detectors, e0 configuration 1+1+2, f0 configuration 1+1+1. vii - command set description (continued) st75c530 - ST75C540 39/84
tdwc tone detector write coefficient tdwc opcode: 1c 00011100 synopsis tdwc write one coefficient of the selected tone detector cell. parameters field byte pos. value definition td_cell 1 4..0 0..13 tone detector cell number td_c_addr 2 7..0 0..b 10 20 30 (1) 40 (1) biquad coefficient energy coefficient static level energy coefficient for relative comparison gain for relative comparison td_coefl 3 7..0 low byte of coefficient td_coefh 4 7..0 high byte of coefficient note 1 : value 30 and 40 of byte 2 are available only for secondary tone detector. tdww tone detector write wiring tdww opcode: 1d 00011101 synopsis tdww write wiring of the selected tone detector cell. parameters field byte pos. value definition td_cell 1 4..0 0..13 tone detector cell number for primary tone detector field byte pos. value definition td_w_addr 2 0 0 1 other biquad and energy input comparator inputs reserved if td_w_addr = 0 (select biquad and energy inputs) field byte pos. value definition td_w_ern 3 0..3f energy estimator signal input td_w_biq 4 0..3f biquad filter signal input if td_w_addr = 1 (select comparator inputs) field byte pos. value definition td_w_cn 3 0..3f negative comparator signal input td_w_cp 4 0..3f positive comparator signal input for secondary tone detector field byte pos. value definition td_4diff 2 7..0 00 01 other relative comparison not enable relative comparison enable reserved td_4_conf 3 7..0 0 mandatory td_4_conf2 4 7..0 c0 e0 f0 other 1+1 configuration 1+1+2 configuration 1+1+1+1 configuration reserved vii - command set description (continued) st75c530 - ST75C540 40/84
tdz tone detector clear cell tdz opcode: 1e 00011110 synopsis tdz clears all internal variables of one tone detector cell including filter local variables and energy estimator. this command must be sent after changing coefficients of a cell to avoid instability. parameters field byte pos. value definition td_cell 1 4..0 0..13 tone detector cell number tgen enable/disable tone generators tgen opcode: 0d 00001101 synopsis enable or disable one of the four tone generator, define the output of the tone generator either line or audio. parameters field byte pos. value definition tone_0_ena 1 0 0* 1 generator #0 disabled generator #0 enabled tone_1_ena 1 1 0* 1 generator #1 disabled generator #1 enabled tone_2_ena 1 2 0* 1 generator #2 disabled generator #2 enabled tone_3_ena 1 3 0* 1 generator #3 disabled generator #3 enabled tone_0_out 1 4 0* 1 generator #0 output to line generator #0 output to audio tone_1_out 1 5 0* 1 generator #1 output to line generator #1 output to audio tone_2_out 1 6 0* 1 generator #2 output to line generator #2 output to audio tone_3_out 1 7 0* 1 generator #3 output to line generator #3 output to audio vii - command set description (continued) st75c530 - ST75C540 41/84
tone predefined tones tone opcode: 0c 00001100 synopsis tone programs the tone generator for the predifined tones. the tone generator #0 and eventualy #1 are reprogrammed with this command. the tone generator #0 and eventualy the #1 are enabled. using a value not in the following table will disable tone generator #0 and #1. parameters field byte pos. value definition tone_select 1 5..0 0 1 2 3 4 5 6 7 8 9 a b c d e f 10 11 12 13 14 dtmf digit 0 dtmf digit 1 dtmf digit 2 dtmf digit 3 dtmf digit 4 dtmf digit 5 dtmf digit 6 dtmf digit 7 dtmf digit 8 dtmf digit 9 dtmf digit a dtmf digit b dtmf digit c dtmf digit d dtmf digit * dtmf digit # answer tone 2100hz tone 1650hz tone 2225hz tone 1300hz tone 1100hz tone_out 1 7 0 1 output on line output on audio xmit start/stop transmission xmit opcode: 01 00000001 synopsis xmit start or stop the transmission of the transmit data. parameters field byte pos. value definition tx_start 1 0 0* 1 stop transmission start transmission vii - command set description (continued) st75c530 - ST75C540 42/84
this appendix is dedicated to the st75c530/540 reporting features. in the following sections the command acknowledge process and the report and status definitions are explained. viii.1 - command acknowledge and report viii.1.1 - command acknowledge process the st75c530/540 features an acknowledge process based on a counter comack. on power- on reset (or init command), this counter's value is set to 0. each time a command is successfully executed by the st75c530/540, the acknowledge counter comack is incremented. this allows a precise monitoring of the command entered and avoids command collision. in the case of a memory reading command (cr, tdrc, tdrw, idt or mr) once the command entered is executed,the reportarea is filled and the acknowledge counter is incremented afterwards. this insures that the controller will read the value corresponding to its request. furthermore, the st75c530/540 resets the value of the comsys register and the interruption it6 is raised. viii.1.2 - reports specification the report section of the dual port ram is dedi- cated to memoryreading. in response to a cr, mr, mri, mrlo, tdrc, tdrw, idt commands, the value read is transferred to the report registers comrep[0..1]. viii - status description assert interrupt it0 set syserr err_iocd set syserr err_iprm execute command clear answer end yes no begin comsys = 0 command exist no yes clear comsys assert interrupt it6 copy answer into comrep assert interrupt it0 increment comack 75c53020.eps figure 16 : command acknowledge process st75c530 - ST75C540 43/84
viii.1.3 - cr command issuing a cr command causes the st75c530/540 to dump a specific memory location in complex mode. this instruction is particularly useful for equalizer state analysis or for software eye-pattern display. the report area has this meaning : rp7 rp6 rp5 rp4 rp3 rp2 rp1 rp0 comrep[0] ip7 ip6 ip5 ip4 ip3 ip2 ip1 ip0 comrep[1] rp0..rp7 is the msb part of the 16-bit value of the real part and ip0..ip7is the msb part of the imaginary part. the cr command insures that the real and imaginary part of the desired complex value are sampled internally at the same time. the address given in the parameter field of cr is the address of the real part. viii.1.4 - mr/tdrc/tdrw/idt/mri/mrlo commands the report issued by the mr/tdrc/tdrw/idt/mri/mrlo commands follow the same rules as for cr. the report meaning is : d7 d6 d5 d4 d3 d2 d1 d0 comrep[0] d15 d14 d13 d12 d11 d10 d9 d8 comrep[1] d0..d15 is the 16-bit value requested by the command. in the case of idt,d15..d12 containsthe productidentification(3 for st75c530,7 for st75c5540), d11..d8 contains the hardware revision identification and d7..d0 contains the software revision identification. viii.2 - modem status viii.2.1 - modem status description the status of st75c530/540 is divided into 4 fields : - the error status byte syserr that provides information about error. this status can trigger an it0 interrupt, - the general status byte status[0] and status[1] that contains all the modem signals. these status bytes can trigger an it4 interrupt, - the quality status staqua, that contains the quality of the received transmission, - the optional status bytes staop[0], staop[1], staop[2] and staop[3], that contains additional information regarding the st75c530/540 operating mode. this default information can be changed to monitor any internal variables using the dosr command. all these informations are updated on a baud basis : mode baud rate (2) (hz) v.32bis/v.32 (ST75C540 only) 2400 v.22bis/v.22/bell 212a (ST75C540 only) 2400 tone 2400 bell 103 (full duplex) 2400 v.21 (full duplex) 2400 v.23 (full duplex) 2400 v.27ter 2400bps 1200 v.27ter 4800bps 1600 (1) v.29 2400 v.17/v.33 2400 v.21 channel 2 2400 handset, coder or decoder modes 1200 notes : 1. in this mode the tone detectors outputs are update 800 times by second. 2. this baud rate defines also, the maximum command rate. each baud time the st75c530/540 looks at the comsys location (address $00) to see if a command have been sent by the host processor. if the content of this location is different from zero the st75c530/540 execute the command. viii - status description (continued) st75c530 - ST75C540 44/84
starting at the adddress $08 the status area have the following format : add. name bit 765 43210 $08 syserr err_rtk - - err_iprm err_iocd err_voco err_rx err_tx $09 status0 sta_109f sta_cpt10 sta_cpt1 sta_cpt0 sta_ring sta_106 sta_107 sta_109 sta_vad $0a status1 sta_dtmf sta_flag sta_clr* sta_rneg sta_hr sta_rtrn* sta_at sta_ccitt sta-tim sta_h $0b staqua - quality $0c staop0 depend on operating mode (see below) $0d staop1 $0e staop2 $0f staop3 * ST75C540 only viii.2.2 - error status the error status changes each time an error occurs. when the st75c530/540 signals an error by setting one of the syserr bit, it generates an interrupt it0. these bits can only be cleared by the host controler using the cse command. the meaning of the different bits of the syserr byte is discribed below : syserr field pos. meaning when set err_tx 0 transmit buffer underflow. loss of synchronisation between the host and st75c530/540 transmit data buffer managment. err_rx 1 receive buffer overflow. loss of synchronisation between the host and st75c530/540 receive data buffer managment. err_voco 2 vocoder buffer underflow (decoder) or overflow (coder). lost of synchronisation between the host and st75c530/540 vocoder buffer management. err_iocd 3 incorrect command err_iprm 4 incorrect parameter for the command err_rtk 7 real time kernel error. st75c530/540 not able to perform all its tasks within the baud period (transmit or receive samples lost). viii - status description (continued) st75c530 - ST75C540 45/84
viii.2.3 - modem general status the modem general status word is composed of two bytes status[0] and status[1]. any bit change can generate an it4 interrupt. using the dsit command allows the selection of the corresponding bit that will generate an interrupt each time they will change. the default pattern is $3f for status[0] and $ff for status[1]. the different bits have the following meaning : status[0] field pos. meaning when set sta_109 sta_vad 0 in fax modem and tonecid modes sta_109 : ccitt circuit 109 (carrier detect). indicates that valid data are received. in coder and decoder modes : vad: voice activity detected sta_107 1 ccitt circuit 107 (data set ready). valid only in fax & data modem modes. sta_106 2 ccitt circuit 106 (clear to send). indicates that the training sequence has been completed and that any data in the transmit buffer will be transmitted. valid only in fax & data modem modes. sta_ring 3 ring detected. a valid ring signal is present at the ring pin. valid only in tones modes. the precise frequency can be read in the optional status byte staop2. sta_cpt0 4 in tone and tonecid modes sta_cpt0: call progress tone detector #0. low pass filter 650hz. sta_cpt1 5 in tone and tonecid modes sta_cpt1: call progress tone detector #1. high pass filter 600hz. sta_cpt10 6 in tone and tonecid modes sta_cpt10: signal in filter #0 is higher than #1. sta_109f 7 in fax modem mode, v.22bis mode* and tonecid mode sta_109f: fast carrier detect. * ST75C540 only status[1] field pos. meaning sta_h 0 transmit synchronisation in progress. valid only in fax & data modem modes. sta_tim* 1 handshake timeout. valid only in data modem mode. sta_ccitt 2 ccitt 2100hz versus 2225hz answer tone detect. valid if sta_at is set. valid only in tone mode. sta_at 3 answer tone (either 2100hz or 2225hz) detected. valid only in tone mode. sta_hr sta_rtrn* 4 sta_hr : receive synchronisation in progress. valid only in fax modem mode. sta_rtrn : remote retrain detec, valid only in v.32bis/v.32/v.22bis data modem modes. sta_reneg* 5 remote rate negotiation detected, valid only in v.32bis/v.32/v.22bis data modem modes. sta_flag sta_clr* 6 sta_flag : v.21 channel 2 flag detect. valid only in fax modem mode and tone mode. sta_clr : remote clear down detected v.32bis/v.32 data modem modes. sta_dtmf 7 dtmf digit detect. the digit itself is available in the optional status byte staop3. * ST75C540 only viii - status description (continued) st75c530 - ST75C540 46/84
viii.2.4 - quality status the quality bytes staquaand staquas monitor an evaluationof the line quality. they are updated once per baud and their value ranges from 127 (perfect quality) to 0 (terrible quality). this value is automaticaly adjusted according to the current receiving mode. refer to the following chart to convert the value of staqua into its bit error rate equivalence. the time constant for staqua is 100ms. the slow quality byte (available on staop1 in fax and data mode except fsk) staquas gives the equivalent quality with a 1 seconde time constant. viii - status description (continued) 1e -3 1e -4 1e -5 1e -6 1e -7 1e -8 1e -9 0 31 63 95 127 staqua ber 1e -2 75c53021.eps viii.2.5 - optional status according to the operating mode of the st75c530/540 the optional status is displaying different informa- tions. the optional status are automatically reprogrammed after each conf command with the address of the variablesto monitor according with the operating mode selected (conf_oper).afterthe conf command the user must overwrite this default programming by using the dosr command. in order to change the default set-up please refer to the aram mapping application noteo (delivered on request according to revision number) to obtain the addresses of the dsp internal variables. viii.2.5.1 - default optional status in all modes except modem while in tone mode the format of the staop word is as follows : optional status words add. name bit 76543210 $0c staop0 tdt7 tdt6 tdt5 tdt4 tdt3 tdt2 tdt1 tdt0 $0d staop1 tdt15 tdt14 tdt13 tdt12 tdt11 tdt10 tdt9 tdt8 $0e staop2 ring_period (1) $0f staop3 tdt19 tdt18 tdt17 tdt16 dtmf_digit (4) notes : 1. ring_period is valid when the bit 3 of the status0 (sta_ring goes high. this value is updated at eac h falling edge of the ring signal. the ring_period value must be multiplied by 2400 to obtain the period in second. 2. tdtx (x in [0..15]) is the output of the 16 tone detectors x (sampling rate 7200hz). 3. tdty (y in [16..19] is the output of the secondary tone detectors (sampling rate 4800hz or 9600hz) with absolute comparison or relative comparison. 4. dtmf_digit is valid when the bit 7 of status1 (sta_dtmf) goes high. this value remains unchanged until a new dtmf digit is detected. st75c530 - ST75C540 47/84
viii.2.5.2 - default optional status in fax mode while in fax modem mode the format of the staop word is as follows : optional status words in modem mode add. name bit 7654321 0 $0c staop0 x x x speed (2)(5) spval (1)(5) $0d staop1 staquas $0e staop2 pnsucs prdets pndets scr1s prs pns p2s p1s $0f staop3 tdt19 tdt18 tdt17 tdt16 dtmf_digit (4) notes : 1. spval is active in v.33 receiver only at the same time as the rising transition of the scr1s signal. when spval is set, it indicates that the speed bits contain the data speed information. 2. speed is valid in v.33 receiver only it can have 2 values, after the scr1s signal goes high : 1000 for 14400bps and 0111 for 12000bps. 3. the staop2 bit reflects the progression of the synchronisation. 4. only valid in v.21 channel 2 receive mode. the staop2 bits have the following meanings : staop2 in fax modem mode name position description p1s 0 unmodulated carrier sequence. optional, used for echo protection. p2s 1 continuous 180 phase reversal sequence pns 2 equalizer trainning sequence prs 3 v.33 and v.17 rate sequence scr1s 4 continuous scrambled 1 sequence pndets 5 turned on after pn sequence detection prdets 6 turned on after pr sequence detection (v.33 and v.17 only) pnsucs 7 turned on after succesfull training of the receive equalizer. when on at the end of the synchronization, the transmition ber is statisticaly bellow 10ppm. viii - status description (continued) st75c530 - ST75C540 48/84
with the following timing : viii - status description (continued) t1 transmit p2 p1 pn r scr1 data t2 t3 t4 t5 t6 sta_h p1s p2s pns prs scr1s (7) t7 receive t8 t7 t8 t8 t8 sta_hr sta_109f p2s prdets pnsucs scr1s sta_109 rxdata pns pndets (1) (2) (8) (6) 75c53022.eps mode t1 (4) t1p (5) t2 t3 t4 t5 t6 t7 t8 unit v.17 192 30 22 107 1240 27 20 5 7 ms v.17 short 192 30 22 107 16 0 20 5 7 ms v.29 192 30 22 53 160 0 20 5 7 ms v.29 short 192 30 22 41 26 0 8 5 7 ms v.27 4800 192 30 22 31 670 0 5 5 7 ms v.27 4800 short 192 30 22 9 36 0 5 5 7 ms v.27 2400 192 30 22 42 895 0 7 6 7 ms v.27 2400 short 192 30 22 12 48 0 7 6 7 ms st75c530 - ST75C540 49/84
transmit scr1 data t10 t11 min sta_h p1s pns prs scr1s receive t13 sta_hr sta_109f prdets pnsucs sta_109 rxdata pns pndets (3) p2s t12 (3) (3) (3) (6) 75c53023.eps mode t10 t11 t12 t13 unit v.17 13 20 8 25 ms v.17 short 13 20 8 25 ms v.29 13 20 8 25 ms v.29 short 13 20 8 25 ms v.27 4800 20 30 8 25 ms v.27 4800 short 20 30 8 25 ms v.27 2400 27 40 8 25 ms v.27 2400 short 27 40 8 25 ms notes : 1. in the case of v.29 or v.27, prs and prdets bits are not active. 2. pnsucs indicates the quality of the rx signal that will give a ber of approximation of 1e -5 . 3. after sending the command sync0, all bits are reset. 4. when using long echo protection tone, otherwise 0. 5. when using short echo protection tone, otherwise 0. 6. sta-106 is set at the end of t6 and reset at the beginning of t10. 7. after sending the command sync1, this bit is set. 8. pnsuc is evaluated twice, first at scr1 detection and further 256 baud (v.29, v.17, v.33 : 106ms ; v .27 4800bps : 160ms ; v.27 2400bps : 212ms) after sta_109. 9. for v.21 channel 2, timing for loss of sta_109 is 25ms and timing for detection of sta_109 is 7ms. 10. for v.21 channel 2 after a stop command, sta_h is set to a1o during 13ms when the last hdlc flag is transmitted. viii - status description (continued) st75c530 - ST75C540 50/84
viii.2.5.3 - default optional status in data modem mode (ST75C540 only) while in data modem mode the format of the staop word is as follows : optional status words in modem mode add. name bit 7654321 0 $0c staop0 x x x speed (2)(5) spval (1)(5) $0d staop1 staquas $0e staop2 hshk_pha $0f staop3 tdt19 tdt18 tdt17 tdt16 not used notes : 1. spvalis active in v.33 receiver only at the same time as the rising transition of the scr1s signal. when spval is set, it indicates that the speed bits contain the data speed information. 2. speed is valid in v.32bis, v.32, v.22bis, v.22, bell 212a and v.33 receiver only with the following meaning : bit 4 bit 3 bit 2 bit 1 data speed 0 0 1 0 1200bps 0 0 1 1 2400bps 0 1 0 0 4800bps 0 1 0 1 7200bps 0 1 1 0 9600bps 0 1 1 1 12000bps 1 0 0 0 14400bps other reserved 3. the staop2 bit reflects the progression of the synchronisation. 4. only valid in v.21 channel 2 receive mode. 5. spvalis active in v.32bis/v.32/v.22bis/v.22 at the end of the training sequence and at least 8 baud before entering data mode. spvaland speed are also updated with each retrain and rate negotiation. 6. the spaop1 bits reflect the progression of the synchronization in data modes. viii - status description (continued) st75c530 - ST75C540 51/84
the staop2 bits have the following meanings in data modem mode : hshk_pha(r) handshake progression counter contains information about the progress of the hadshake in v.32 and v.22bismodes. this 8-bit value is available in staop2 in modem mode. it can be read to examine the progressio of the handshake and it contains normal values and error values as below : autobaud orig mode event hshk_pha value wait answer tone wait end answer tone not autobaud and waiting usc1 autobaud waiting ac or usc1 $01 $02 $03 $04 autobaud answ mode event hshk_pha value waiting hsk command generating answer tone generating silence $10 $11 $12 v.32 orig mode event hshk_pha normal value hshk_pha error value ac_det ac/ca det ca/ac det no ac det s_det sb_det r1_det s_det sb_det r3_det e_det data_mode $20 $21 $22 $23 $24 $25 $26 $27 $28 $29 $2a $30 $1 $2 $b for rtn, $c for rtn $4 $5 $6 $7 $8 $9, $d no r5 det after rrn $a v.32 answ mode event hshk_pha normal value hshk_pha error value aa_det aa/cc det no cc det s_det sb_det2 sb_det r2_det e_det data_mode $40 $41 $42 $43 $44 $45 $46 $47 $50 $8 for rtn, $9 for rrn $1 $2 $3 $4 $5 $6, $a if no r det after rrn $7 v.22bis orig mode event hshk_pha normal value hshk usc1_det scr1_det s1_det data_mode $60 $61 $62 $63 $70 v.22bis answ mode event hshk_pha normal value hshk scr1_det s1_det data_mode $80 $82 $83 $90 viii - status description (continued) st75c530 - ST75C540 52/84
ix - tone detectors z -1 c0 c5 2 z -1 z -1 z -1 2 cb c7 c8 c9 ca c1 c2 c3 c4 z -1 in out c6 75c53024.eps figure 17 : biquadratic iir filter ix.1 - overview the general purpose st75c530/540 tone detec- tors block is a powerful module that covers a lot of applications : - call progress tone detection, fully programmable for all countries, - fax, voice, data automatic detection, - call waiting detection, while in vocoder or data mode. ix.2 - description the primary tone detector block is a set of 16 identical cells. each cell is composed of a double biquadratic filter, a power estimator section, a static level and a level comparator. each biquadratic filter, power estimator and static level can be programmed using a complete set of commands ( tdrc , tdrw , tdwc , tdww , tdz ). the wiring between the different cells can be de- fined by the user, using the associated command allowing a wide range of applications. the sampling frequency is 7200hz, allowing detec- tion of signals less than 3300hz.the level of detec- tion is programmable from -6dbm down to -51dbm. the 16 comparator outputs give, on a baud basis, the information into two 8 bits words tonedet0 (for cells number 0 to 7) and tonedet1 (for cells number 8 to f). these tonedet variables can be accessed using a mri command or, more easily, monitored on a baud basis using the dosr com- mand. the 16 primary tone detectorsare initializedeach time entering the tone mode. however the previous coeffi- cient values could be kept using a mw command. the secondary tone detector have been added to the st75c530/540. the filter structure is the same as the primary tone detector. the sampling rate is 4800hz allowing detection of signal less than 1800hz by defaultprogramming or with a modc command, the sampling rate is 9600hz allowing detection of signal less than 3300hz. the level of detection is programmable from -6dbm down to -51dbm. in order to increase the reliability of the detection, using a tdww com- mand, 2 comparisonsare provided,one with a fixed level (absolute) or with the receive signal (relative). the 4 secondary tone detectors are initialiazed each time entering the tone mode. however the previous coefficient values could be kept using a conf command. thecommandtdrc, tdwc, tdww, tdrw, tdz with the td_cell parameter of 0x10, 0x11, 0x12 or 0x13 can be used to program these filters. ix.2.1 - biquadratic filters each biquadratic filter is a double regular section that can perform any transfer function with 4 poles and 4 zeros. this routine is run on a sample basis. the corresponding transfer function is : out input = c0 ? c5 + 2 ? c3 ? z - 1 + 2 ? c4 ? z - 2 1 - 2 ? c1 ? z - 1 - 2 ? c2 ? z - 2 ? c6 ? cb + 2 ? c9 ? z - 1 + 2 ? ca ? z - 2 1 - 2 ? c7 ? z - 1 - 2 ? c8 ? z - 2 ? z - 1 note : all coefficients are coded on 16 bits 2's complement in the range +1, -1 (q15). to avoid the possibility of overflow the user must check that the internal node must not be higher that 0.5 (in q15 representation). st75c530 - ST75C540 53/84
ix.2.2 - power estimation the power estimation cell is needed to measure the amplitude of the different tones. it is run on a sample basis. ix - tone detectors (continued) z -1 in out abs(.) p1 + z -1 75c53025.eps figure 18 : power estimator the corresponding transfer function is : out = | input | ? z - 1 ? p1 1 - ( 1 - p1 ) ? z - 1 ix.2.3 - static level a single threshold level is associated with each cell. it canbe use to comparethe output of a power estimation with an absolute value. ix.2.4 - comparator the comparator computes, on a baud basis, the differenceof the signal on its positive and negative inputs. if the result is higher that zero it sets the corresponding bit into the tonedet[0..1] word; if not it clear this bit. ix.2.5 - wiring the user must specify the connection (wiring) be- tween the input/outputof the filter, the input/output of the power estimator, the output of the static levels and the two inputs of the comparators. the output signals have an absolute address: node address signal name address description ground 00 signal always equal to 0000 rxsig 01 receive signal from the analog front end rxsig2 02 receive signal multiplied by 2 rxsig4 03 receive signal multiplied by 4 04..0f reserved filter[0..f] 10..1f biquadratic filter outputs power[0..f] 20..2f power estimator outputs level[0..f] 30..3f static levels the user will specify the inputs of the filters, power and comparator. at leastone input must comefrom the rxsig (node 01, 02 or 03). it is mandatory to connect all unused cell inputs to the ground signal (node 00). st75c530 - ST75C540 54/84
rx signal ground @00 @01 @02 @03 d3 d4 d5 tonedet0 d6 d7 d2 d1 d0 @10 @20 @30 @11 @21 @31 @12 @22 @32 @13 level #3 power #3 @23 @33 @14 @24 @34 @15 @25 @35 @16 @26 @36 @17 @27 @37 2 2 biquadratic filter #0 biquadratic filter #1 biquadratic filter #2 biquadratic filter #3 biquadratic filter #4 biquadratic filter #5 biquadratic filter #6 biquadratic filter #7 level #0 power #0 level #1 power #1 level #2 power #2 level #4 power #4 level #5 power #5 level #6 power #6 level #7 power #7 comp. #7 comp. #6 comp. #5 comp. #4 comp. #3 comp. #2 comp. #1 comp. #0 75c53026.eps figure 19 : tone detector wiring address (first half) ix - tone detectors (continued) st75c530 - ST75C540 55/84
d3 d4 d5 tonedet1 d6 d7 d2 d1 d0 @18 @28 @38 @19 @29 @39 @1a @2a @3a @1b @2b @3b @1c @2c @3c @1d @2d @3d @1e @2e @3e @1f @2f @3f level #9 comp. #f comp. #e comp. #d comp. #c comp. #b comp. #a comp. #9 comp. #8 biquadratic filter #f biquadratic filter #e biquadratic filter #d biquadratic filter #c biquadratic filter #a biquadratic filter #b power #8 power #9 power #a power #b level #b power #c power #d power #e level #e power #f level #f level #d level #c level #a level #8 biquadratic filter #8 biquadratic filter #9 75c53027.eps figure 20 : tone detector wiring address (second half) ix - tone detectors (continued) st75c530 - ST75C540 56/84
and or tdt17 relative -td4diff or tdww 1100 00c0 fourth order iir filter #16 pow () #16 level #16 pow () #20 gain #16 comparator #16 comparator #16 input signal fourth order iir filter #17 pow () #17 level #17 pow () #20 gain #17 comparator #17 comparator #17 and or tdt16 relative -td4diff or tdww 1001 00c0 absolu absolu 75c53028.eps figure 21a : secondary tone detector configuration (2 tone detectors 1 + 1) and or tdt17 relative -td4diff or tdww 1100 00e0 fourth order iir filter #16 pow () #16 level #16 pow () #20 gain #16 comparator #16 input signal fourth order iir filter #17 pow () #17 level #17 pow () #20 gain #17 comparator #17 comparator #17 and or tdt16 relative -td4diff or tdww 1001 00e0 and or tdt18 relative -td4diff or tdww 1200 00e0 fourth order iir filter #18 pow () #18 level #18 pow () #20 gain #18 comparator #18 comparator #18 fourth order iir filter #19 comparator #16 absolu absolu absolu 75c53029.eps figure 21b : secondary tone detector configuration (3 tone detectors 1 + 1 + 2) ix - tone detectors (continued) st75c530 - ST75C540 57/84
and or tdt17 relative -td4diff or tdww 1100 00f0 fourth order iir filter #16 pow () #16 level #16 pow () #20 gain #16 comparator #16 comparator #16 input signal fourth order iir filter #17 pow () #17 level #17 pow () #20 gain #17 comparator #17 comparator #17 and or tdt16 relative -td4diff or tdww 1001 00f0 absolu absolu and or tdt18 relative -td4diff or tdww 1201 00f0 fourth order iir filter #18 pow () #18 level #18 pow () #20 gain #18 comparator #18 comparator #18 absolu and or tdt19 relative -td4diff or tdww 1300 00f0 fourth order iir filter #19 pow () #19 level #19 pow () #20 gain #19 comparator #19 comparator #19 absolu 75c53030.eps figure 21c : secondary tone detector configuration (4 tone detectors 1 + 1 + 1 + 1) ix - tone detectors (continued) st75c530 - ST75C540 58/84
biquadratic filter #3 level #3 power #3 power #4 power #5 level #4 level #5 comp. #4 comp. #3 comp. #5 d3 d4 d5 biquadratic filter #5 biquadratic filter #4 rx signal ground @00 @01 @02 @03 @13 @14 @15 @23 @33 @24 @34 @25 @35 tonedet0 2 2 75c53031.eps figure 22 : wiring example ix.3 - example ix - tone detectors (continued) hereunder is an example of programming a single tone detection (using cell #3) and a complex dif- ferential tone detection (using cell #4 and #5). bit 3 of the tonedet variable will be triggered each time the energy of that filtered signal is higher than static level number 3. bit 4 of the tonedet variable will be on each time a receive signal has an energy higher than the static level number 4. bit 5 will be on only when the filtered (filter section 4 and 5) received signal higher than the energy of the wide-band signal number 4 ; this prevents triggering on noise. program cell #3 : tdww03001301 connect received signal to filter and filter to energy. tdww03013323 connect level to comparator neg input and energy to pos input. program cell #4 and #5 : tdww04000101 connect received signal to filter and energy. tdww04013424 connect level to comparator neg input and energy to pos input. tdww05001514 connect filter#4 output to filter and filter to energy. tdww05012425 connect wide-band energy to neg input and energy to pos input. st75c530 - ST75C540 59/84
x - parallel data exchange hdlc uart tx buffers modul. demod. h rx buffers tx rx it2 it3 telephone line control data host interface hdlc uart 75c53032.eps figure 23 x.1 - overview while transmiting (respectively receiving) data to (from) the telephone line data are exchanged be- tween the host and the st75c530/540. two totaly independent channels are provived for transmit and receive data. even while using half duplex modes of operation, the transmitted data comes from the transmit buffers and the receive data arrives in the receive buffers. two independent interrupts, it2 (for transmit) and it3 (for receive) are available for synchronizing the st75c530/540 and the host. an additional it0 interruptwill signal the errorsin the synchronization mechanism. the equivalent data flow is as follows (see fig- ure 20). the st75c530/540 has a buit-in hdlc capability. this feature automatically performs hdlc fram- ing/deframing, crc generation/detection and a0o insertion/deletion. the st75c530/540 have also uart capability, the format of data is selected by the form command described bellow. x.2 - transmit buffers two identical buffers are provided to exchange the data between the host interface and the st75c530/540. when the host is writing data into a buffer, the st75c530/540 is transmitting the other one. after that, both the host and the st75c530/540switch to use the other buffer. this mechanism, called adouble-bufferingo, ensures that the host has the maximum time to fill one buffer. the dual ram area associated with the transmit buffers is as following table. name address description dttbs0 $2e buffer 0 status byte dttbs0 [0] $2f buffer 0 data byte 0 dttbs0 [1] $30 buffer 0 data byte 1 dttbs0 [2] $31 buffer 0 data byte 2 dttbs0 [3] $32 buffer 0 data byte 3 dttbs0 [4] $33 buffer 0 data byte 4 dttbs0 [5] $34 buffer 0 data byte 5 dttbs0 [6] $35 buffer 0 data byte 6 dttbs0 [7] $36 buffer 0 data byte 7 dttbs1 $37 buffer 1 status byte dttbs1 [0] $38 buffer 1 data byte 0 dttbs1 [1] $39 buffer 1 data byte 1 dttbs1 [2] $3a buffer 1 data byte 2 dttbs1 [3] $3b buffer 1 data byte 3 dttbs1 [4] $3c buffer 1 data byte 4 dttbs1 [5] $3d buffer 1 data byte 5 dttbs1 [6] $3e buffer 1 data byte 6 dttbs1 [7] $3f buffer 1 data byte 7 bit 0 (lsb) of the buffer 0 data byte 0 is the first in time to be transmited. according to the data format, the status byte of a buffer has different meanings. however a value of 0 signals to the host that a buffer is empty. this value is set by the st75c530/540 each time it has emptied the buffer. after having used one buffer, the host must select the other buffer for the next operation. the host must start with the buffer 0 as soon as the st_106 signal goes on and before the xmit 1 command is sent. a mechanism of interruption ( it2 for transmit) is associated with the data buffer managment. each time a buffer is emptied by the st75c530/540 it generates an interrupt. st75c530 - ST75C540 60/84
x.3 - receive buffers symetrically two identical buffers are provided to exchange receive data between the st75c530/540 and the host processor. while the st75c530/540 is filling one of the buffers with the receive bits, the host processor is reading the other buffer. as soon as the host has emptied a buffer it frees it by writing 0 in the buffer status byte. the dual ram area associated with the receive buffers is as following table. name address description dtrbs0 $1c buffer 0 status byte dtrbs0 [0] $1d buffer 0 data byte 0 dtrbs0 [1] $1e buffer 0 data byte 1 dtrbs0 [2] $1f buffer 0 data byte 2 dtrbs0 [3] $20 buffer 0 data byte 3 dtrbs0 [4] $21 buffer 0 data byte 4 dtrbs0 [5] $22 buffer 0 data byte 5 dtrbs0 [6] $23 buffer 0 data byte 6 dtrbs0 [7] $24 buffer 0 data byte 7 dtrbs1 $25 buffer 1 status byte dtrbs1 [0] $26 buffer 1 data byte 0 dtrbs1 [1] $27 buffer 1 data byte 1 dtrbs1 [2] $28 buffer 1 data byte 2 dtrbs1 [3] $29 buffer 1 data byte 3 dtrbs1 [4] $2a buffer 1 data byte 4 dtrbs1 [5] $2b buffer 1 data byte 5 dtrbs1 [6] $2c buffer 1 data byte 6 dtrbs1 [7] $2d buffer 1 data byte 7 the bit 0 (lsb) of the buffer 0 data byte 0 is the first received bit in time (the oldest). according to the data format, the status byte of a buffer has different meaning. however a value of 0 signals to the st75c530/540that a buffer is empty. this value is set by the host each time it has emptied the buffer. after having used one buffer, the host must select the other buffer for the next operation. the host must start with the buffer 0 as soon as the sta_109 signal goes. a mechanism of interruption ( it3 for receive) is associated with the data buffer managment. each time a buffer is filled by the st75c530/540 it gen- erates an interrupt. x.4 - interruption two interrupt signals are provided in order to syn- chronize the data buffer exchanges. it2 is asso- ciated with the transmit buffer mechanism and it3 with the receive buffer mechanism. in order to enable these interrupts, the host proc- essor must set the bit 2 (for it2 ) and the bit 3 (for it3 ) of the itmask register to 1. it must also set the bit 7 of the itmask register to 1 in order to globally enable all the selected sources of interrup- tion. when an interrupt occurs (low level on sintr pin) the user must read the itsrcr register to deter- mine the source of the interrupt, either it2 for tx (if the bit 2 is 1) or it3 for rx (if the bit 3 is 1). once the interrupt has been serviced, the host must acknowledge it by writing a $00 value into the register itres2 for it2 ,or itres3 for it3 . these registers have the following address : name address type description itres2 $42 write only clear it2 itres3 $43 write only clear it3 itmask $4f read/write interrupt mask itsrcr $50 read only interrupt source notes : 1. the st75c530/540 does not check that the interrupt has been acknowledged. 2. even if the host does not use the interruption, the st75c530/540 will set the bit 2 (for it2 ) and/or bit 3 (for i t3 ) of the itsrcr . 3. the st75c530/540 uses only the data buffer status bytes to detectoverrun or underrun error. these errors are reported into the syserr byte, and could generate an interrupt i t0 . the equivalent schematic is : see figure 21. the interrupt mechanism assumes that the host processor uses a level sensitive interrupt (active low). the flow chart of the host interrupt service routine looks generaly like figure 22. x.5 - data format different formats of data can be transmitted/re- ceived to/from the telephone line. these formats can be selected when entering the data mode by using the form command. the format of the data can be changed,on the fly in the data mode during the same communication, by sendinga different form commandat anytime. note that for full duplex operation the data for- mat is the same for the transmitter and the re- ceiver. x - parallel data exchange (continued) st75c530 - ST75C540 61/84
sintr 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 r s q (rx buffer filled) itres 3 (write only) r s q (tx buffer emptied) itres 2 (write only) from ST75C540 dsp itsrcr (read only) itmask (read write) 75c53033.eps figure 24 no yes =0 no yes return it read itsrcr mask unwanted bits bit 2 = 1 execute it_transmit write 00 into itres2 no yes bit 3 = 1 execute it_receive write 00 into itres3 (other interrupts) execute tx buffer management reset it2 execute rx buffer management reset it3 if all sources served return from interrupt check only the interrupt sources that we want to manage under interrupt 75c53034.eps figure 25 x - parallel data exchange (continued) st75c530 - ST75C540 62/84
x.6 - form command the form command allows the selection of the data format. the parameter syntax is as follows : field byte pos. value definition x_sync 1 2..0 000* 001 010 011 100 synchronous format transmit continuous a1o (1) hdlc framming transmit continuous o0o (1) uart x_anbit 2 1..0 00 01 7 bit per character 8 bit per character x_apar 2 3..2 00 01 10 no parity even parity odd parity x_astop 2 5 0 1 1 stop bit(1) 2 stop bit(1) note : 1. transmit only x.6.1 - synchronous mode the synchronous mode is the default mode, if no form command is used. the transmitter reads the bits in the dual ram buffer dttbfx (starting with the bit 0 of byte 0 of buffer 0) and send them over the telephone line. the buffer status byte dttbsx contains the num- ber of data bytes to transmit. the receiver write the received bits coming from the telephone line and write them into the dual ram buffer dtrbfx (startingwith the bit 0 of the byte 0 of thebuffer0). the bufferstatusbyte dtrbsx contains the number of data bytes received (generaly 8). the time between each it2 interrupts(or it3 ) is equal to 64-bit if the number of data bytes is set to 8. the host has the full 64 bits time to serve the interrupt : bit rate (bps) interrupt time (ms) 14400 12000 9600 7200 4800 2400 1200 300 75 4.4 5.3 6.6 8.8 13.3 26.6 53.3 213.3 853.3 x.6.2 - hdlc mode the hdlc format can be used for t.30 or ecm implementations x.6.2.1 - hdlc transmit thehdlc transmitter performsthe following tasks : - flag generation (7e) while in inter-frame. - flag generation (7e) at the begining of a frame. - zero insertion (after 5 consecutive a1o). - crc16 computation. - crc16 transmission at the end of a frame. - flag generation (7e) at the end of a frame. - abort frame. - programmable number of starting flags. - programmable number of inter frame flags. - programmable number of ending flags. the buffer status byte dttbsx defines the frame type, and the number of data bytes to transmit. x.6.2.2 - hdlc receive the hdlc receiver performs the following tasks : - flag recognition. - opening flag recognition. - zero deletion. - crc16 computation. - crc16 check ; error crc16 detection. - closing flag recognition. - abort frame detection. - received crc. the bufferstatusbyte dtrbsx containsthe frame type, the number of data bytes and the error report if any. the errors detected are : - crc16 error : wrong crc received. - non byte-alligned frame : the number of data bits betweenthe begining ofthe frame and theend of the frame (after azeroo deletion)is not a byte- multiple. - aborted frame : more that 6 consecutive a1o re- ceived. x.6.3 - uart mode in the uart mode the buffers contains only one character to transmit or received. the worse case of interruptrate isobtained with the lower character bit length (7bit of data, no parity and 1 stop bit) and is provided in the following table. bit rate (bps) interrupt time (ms) 14400 12000 9600 7200 4800 2400 1200 300 75 0.41 0.41 0.82 1.25 1.64 3.75 7.5 30 120 x.6.3.1 - uart transmit theuart transmitter performsthe following tasks : - start bit generation. - parity computation. - stop bit generation. - break generation. x.6.3.2 - uart receive the uart receiver performs the following tasks : - start bit recognition. - parity checking. - stop bit checking. - break detection. x - parallel data exchange (continued) st75c530 - ST75C540 63/84
form 3 xmit 1 xmit 0 xmit 1 form 2 xmit 0 sta_106 data transmitted commands : 1 0 $7e 10 1 75c53035.eps figure 26 xi - transmitting data in parallel mode xi.1 - description xi.1.1 - xmit command the xmit command works like a cts signal for the parallel data process. when xmit is off, the st75c530/540 transmits continuous a1o. when on the st75c530/540trans- mits data in accordance with the form command and starts to manage the data buffer. this command can be sent at any time, while in data mode (see table below). xi.1.2 - form command the form command can be sent at any time to redefine the current format. the effect will take place only when xmit is on. here is a formal example showing the relationship between xmit , and form commands (see fig- ure 26). xi.1.3 - stop command the stop command is used, at the end of the transmission, to stop sending the carrier on the telephone line. prior to the stop command the user must have stop the parallel transmition with a xmit off com- mand. when the current data buffer will be totaly transmit- ted, and that no more buffers will be available, that is to said both dttbf0 and dttbf1 will be $00 (equivalent to an underrun condition). xi.1.4 - timing here are regular sequences to stop properly the transmition (see figure 27). field byte pos. value definition tx_start 1 0 0 * 1 (off) send continuous a1o (**) . (on) send data according with the format defined in the form command. ** the xmitoff command takes effect only when the two transmit buffers are empty : dttbf0 and dttbf1 equal to $00. feed last buffer xmit 0 stop feed last buffer xmit 0 stop data transmitted sta_106 data transmitted sta_106 (ignored until here) (ignored until here) $7e crc16 last buffer last buffer case # 1 synchronous format case # 2 hdlc format case # 3 uart format 1 xmit 0 stop data transmitted sta_106 (ignored until here) last buffer 1 1 75c53036.eps figure 27 st75c530 - ST75C540 64/84
xi - transmitting data in parallel mode (continued) xi.1.5 - fsk full duplex mode in fsk full duplex mode the parallel mode as- sumes that the bit time duration is the nominal bit rate. each bit element from the transmit buffer is main- tained during the full bit time. the nominal bit clock is defined as follows : fsk standard nominal transmit bit rate (hz) (1) v.21 300 bell 103 300 v.23 originate 75 v.23 answer 1200 note 1 : t he accur acy of the b i t cl ock is given by t he st75c530/540 oscillator, and must better than 100ppm. xi.2 - modem flow chart when data mode, each time the st75c530/540 need a bit to transmit it executes the following routine (see figure 28). where x starts with the value 0 and toggle thereafter between 1 and 0. xi.3 - host flow chart here after are flowcharts to : - establish a v.29 transmission - send synchronous continuous a$aa, $55, $aa, $55, ...o sequence.the managmentof the buffers are done under interrupt. - stop properly the transmition. no yes begin read bit in internal buffer internal buffer empty select next dual ram buffer x no yes dttbsx = 0 move dttbfx data to internal buffer clear dttbsx raise it2 interrupt return return signal error into err_tx raise it0 interrupt select dual ram buffer x = 0 return 75c53037.eps figure 28 establish a v.29 transmition and send the very first buffer (see figure 29). conf 0f 08 00 01 hshk no yes sta_106 = 1 form 00 (opt) xmit 1 fill first buffer select v.29 9600bps start v.29 sequence wait until end of training format synchronous fill the first buffer # 0 start to transmit the first buffer fill first buffer write aa, 55 ... into dttbf [0..7] write 08 into dttbfs0 select next buffer ibuf = 1 tx_completed = false enable it2 itmask = 0 x 84 ret subroutine : 75c53038.eps figure 29 st75c530 - ST75C540 65/84
these flowcharts show two cpu variables labeled ibuf and tx_completed, they are necessary for the understanding of the mechanism, but there is different manners to implement it. these two vari- ables have the following meanning : - ibuf : thisis the numberof the dualram buffer currently in use by the host processor. it starts with 0 and then alternate 1, 0, 1, 0, ... - tx_completed : this is a flag to dialog with the interrupt process in order to stop properly the transmition. the other buffers are sent under interrupt control (refer to the interrupt flow chart, figure 30). to stop properly the transmition, without loss of data (see figure 31). xi - transmitting data in parallel mode (continued) return execute_it_transmit no yes tx_completed ? no yes ibuf = 1 write aa, 55, ... into dttbf1 write 08 into dttbs1 ibuf = 0 write aa, 55, ... into dttbf0 write 08 into dttbs0 ibuf = 1 (1) (1) 75c53039.eps figure 30 xmit 00 stop tx_completed = true no yes sta_106 = 1 stop sending parallel data (delayed) stop signal semaphore with interrupt wait until last buffer is transmitted and ccitt stop sequence completed 75c53040.eps figure 31 xi.4 - error detection error occurs when the st75c530/540 need some bitsfrom the transmitbuffer dttbsx and this buffer is empty. this condition is called aunderflowo. this error is signaled in the bit err_tx of the syserr byte, and generates an interrupt it0 .to clear the error a cse 01 command must be issued. an underflow contition occurs when : - in synchronous mode: the host processor afor- getso to feed the current dttbsx buffer. - in hdlc mode: when, while inside a frame, the host processor aforgetso to feed the current dttbsx buffer. an abort frame is transmitted in place of the regular buffer. - this condition cannot append in uart mode. when an underflow condition occur the host must restart the whole parallel initialization, as explained above. xi.5 - synchronous mode xi.5.1 - description in synchronousmode the st75c530/540transmits the bits contained in the dual ram buffer without any modification. it starts with the bit 0 of the dttbf0[0] byte. xi.5.2 - status word format the transmit status bytes dttbs0 or dttbs1 have the same following meaning(see table below). dttbsx in synchronous mode field pos. value definition buff_leng 3 .. 0 0 1 2 .. 8 other buffer empty. 1 byte to transmit ( dttbfx[0] ). 2 bytes to transmit ( dttbfx[0] and dttbfx[1] ). .. 8 bytes to transmit ( dttbfx[0 .. 7] ). not allowed. other 7 .. 4 0 reserved, must be 0. this status byte must be written by the host, after filing the corresponding data buffer dttbfx[0..7] with the right number of data bytes to transmit. this status byte is cleared by the st75c530/540, just before generating the it2 interrupt. st75c530 - ST75C540 66/84
xi.6 - hdlc mode xi.6.1 - description in hdlc mode the st75c530/540 transmits the data bytes contained into the dual ram buffer packed inside an hdlc frame. the mechanism is as follows : - while the host has no frame to transmit, that is: as long as dttbsx equals $00, the st75c530/540 transmits the hdlc flag $7e. - when the host wants to send some data, it feeds the buffer with some data bytes to transmit (be- tween 1 and 8) and set the buff_sfrm bit in the dttbsx status buffer. at that time the st75c530/540 start sending data contained in the buffer, computin the crc and performing azero intertiono if needed. - when the host wants to send additional data (within the same frame) it feeds the buffers just like in synchronous mode. if an underflow condi- tion occurs, the st75c530/540 will abort the frame by sending 8 consecutive a1o, and the host must restart the whole parallel initialization. - when the host wants to close a frame, it set the buff_efrm bit in the dttbsx status buffer. at that time the st75c530/540 will send the con- tents of the buffer, then send the crc and an hdlc closing flag $7e. - if the host, wants to abort a frame (while sending a frame)it setthe buff_frab bit in the dttbsx status buffer.at thattime, as soon as the last buffer will be transmitted, the st75c530/540 will send 8 consecutive a1o and wait for the next buffer. xi.6.2 - status word format dttbsx in hdlc mode field pos. value definition buff_leng 3 .. 0 0 1 2 .. 8 other buffer empty. 1 byte to transmit ( dttbfx[0] ). 2 bytes to transmit ( dttbfx[0] and dttbfx[1] ). .. 8 bytes to transmit ( dttbfx[0 .. 7] ). not allowed. buff_sfrm 4 0 1 data stream. start of frame : the buffer is a beginning of frame. buff_efrm 5 0 1 data stream. end of frame : the buffer will be followed by the transmission of the crc and closing flag. buff_frab 6 0 1 data stream. abort frame : 8 consecutive a1o will be transmitted (whatever buff_leng is). other 7 0 reserved, must be 0. notes : 1. a buffer can have buff_sfrm and buff_efrm s et in the same dttbsx byte, this means that the frame transmitted is short (between 1 and 8 bytes long). 2. an ending frame (with buff_efrm set) must have at least one byte of data to transmit. xi - transmitting data in parallel mode (continued) transmitted data buff_frab buff_sfrm buff_efrm buff_leng (buff_data) $7e d0 crc d1 d2 d3 062 8 5 $7e crc crc crc $7e $7e $7e d0 d1 d2 d3 000 75c53041.eps figure 32 xi.6.3 - single short frame (see figure 32) st75c530 - ST75C540 67/84
xi.6.4 - long frame xi - transmitting data in parallel mode (continued) transmitted data buff_frab buff_sfrm buff_efrm buff_leng (buff_data) $7e 08 5 crc $7e d0 d1 d2 d3 0 8 4 d0 d1 d2 d3 75c53042.eps figure 33 xi.6.5 - abort frame transmitted data buff_frab buff_sfrm buff_efrm buff_leng (buff_data) $7e d0 d1 d2 d3 0 $7e d5 0 abort d4 d0 d1 d2 d3 d5 d4 x 5 88 x 68 8 75c53043.eps figure 34 xi.6.6 - abort due to underflow transmitted data buff_frab buff_sfrm buff_efrm buff_leng (buff_data) $7e d0 d1 d2 d3 0 abort $7e d4 d5 d0 d1 d2 d3 d4 d5 err_tx (1) (2) (3) 58 8 0 6 88 75c53044.eps figure 35 where : 1. the underflow condition appears when the st75c530/540 needs, inside a frame, some bytes to transmit and that the corresponding buffer is empty. 2. the err_tx bit is cleared with a cse 01 command. 3. after an underflow condition restart the initialization of the parallel mode and use the buffer number 0. st75c530 - ST75C540 68/84
xi - transmitting data in parallel mode (continued) xi.6.7 - hdlc special timming data transmitted 7e..7e 7e data crc _nhfbf 7e..7e 7e crc _nhfcf 7e 7e..7e _nhfst time to fill the buffer 0 (otherwise extra flags added) time to fill the buffer 1 time to fill the buffer 0 data time to fill the buffer 1(otherwise extra flags added) time to fill the buffer 0 it tx it tx it tx it tx it tx form 2 xmit 1 xmit 0 stop 75c53045.eps figure 36 a set of global variables allows the programmation of the number of flags (7e) generated by the st75c530/540 : - _nhfbf : number of flags before the first frame. - _nhfcf : number of flags between frames. - _nhfst : number of flags after the last frame. the default value for all these variables is 0, the programming range is from 0 to 7fff (32767). these varaibales must be modified with a mw or mwi command (see figure 36). xi.7 - uart mode description in uart mode the st75c530/540 transmits the data character contained into the dual ram buffe. the mechanism is as follows : - while the host has no character to transmit, that is: as long as dttbsx equals $00, the st75c530/540 transmits continuous a1o. - when the host wants to send a chacarter,it feeds the buffer with the character to transmit. - the st75c530/540 start to send a stop bit (a0o) then the charactercontainedin the buffer,comput- ing the parity. it send the parity bit, if needed, and the stop bits (1 or 2 according with the form command). - if the user wants to send a break signal, he has to set the buff_ubrk bit within the correspond- ing status word ( dttbsx ). a break signal is defined as a totaly null character with all stop bits duration maintained to a0o (e.g: if format is 7 bit, even parity and 2 stop bit, break is a o0o durring 10 bit). multiple continuous breaks (a0o continu- ous signal) can be send by using consecutive buffers with buff_ubrk set to 1. xi.7.1 - status word format dttbsx in uart mode field pos. value definition buff_leng 3 .. 0 0 1 other buffer empty. 1 character to transmit ( dttbfx[0] ). not allowed. buff_ubrk 6 0 1 normal character. break signal : a complete a0o character with all stop bits equal to o0o. other 7 0 reserved, must be 0. st75c530 - ST75C540 69/84
xii - receiving in parallel mode xii.1 - description when the sta_109 (cd) signal goes on, the st75c530/540 will write received data into the dual ram buffer dtrbs0 at first. xii.1.1 - initialization the host processor must enable the it3 receive interrupt first. then it must empty the two dtrbs0 and dtrbs1 registers by writting $00 at these locations. as soon as the first it3 interrupt appears, the host must proceed with the dtrbs0 buffer. xii.1.2 - loss of carrier each time a loss of carrier appears the st75c530/540 stops updating the data buffer. if the carrier reappers the host must proceed again with the initialisation sequence. xii.1.3 - fsk synchronization the fsk full duplex demodulator uses an algo- rithm based on the transitions of the received sig- nal. the synchronization mechanism is adjusted with each signal transiton in order to sample the demod ulated signal at the middle of the bit (see figure 37). xii.2 - modem flow chart when in parallel data mode, each time the st75c530/540 has receive some bit of data it executes the following routine (see figure 38). where x start with the value 0 and toggle between 1 and 0. demodulated signal sample time receive bit 01 00 1 001 01 75c53046.eps figure 37 no yes begin write bit in internal buffer internal buffer full select next dual ram buffer x no yes dtrbsx = 0 move data from internal buffer to dtrbfx write dtrbsx raise it3 interrupt return return signal error into err_rx raise it0 interrupt select dual ram buffer x = 0 return 75c53047.eps figure 38 xii.3 - host flow chart hereafter are flowcharts to : - establish a v.29 reception. - receive synchronous data. this task is per- formed under interrupt. - handle properly some temporary loss of carrier. st75c530 - ST75C540 70/84
establish the reception (see figure 39). xii - receiving in parallel mode (continued) conf 0f 08 00 01 sync1 no yes sta_109 = 1 form 00 (opt) select v.29 9600bps arm v.29 receiver wait until v.29 carrier detected format synchronous clear the first buffers #0 and #1 in case of lost of carrier while in data mode clear first buffer write 00 into dtrbfs0 write 00 into dtrbfs1 select next buffer ibuf = 0 enable it3 itmask = 0 x 88 ret subroutine : clear first buffer no yes sta_109 = 0 75c53048.eps figure 39 notes : 1. at that step the host can check that the corresponding dtrbsx buffer is full (different from $00), otherwise it is an error. 2. this means read buff_leng bytes, inside the receive buffer dtrbfx starting from location dtrbfx[0] to dtrbfx[buff_leng - 1] . in synchronous mode, the buff_leng isalways 8 bytes, except when a sta_109 lost appears in the middle of the buffer. return no yes ibuf = 1 read dtrbs1 extract buff_leng ibuf = 0 execute_it_receive read dtrbf1 data buff_leng times (2) write 00 into dtrbs1 read dtrbs0 extract buff_leng ibuf = 1 read dtrbf0 data buff_lengtimes (2) write 00 into dtrbs0 (1) (1) 75c53049.eps figure 40 these flowcharts show one cpu variable labeled ibuf which is necessary for the understanding of the mechanism, but there are different manners to implement it. - ibuf : thisis the number of the dual ram buffer currently in use by the host processor. it starts wit 0 an then alternates 1, 0, 1, 0, ... the received bits are read by an interrupt routine (see figure 40). xii.4 - error detection error occurs when the st75c530/540 has re- ceived some bits and that the buffer dtrbsx is not empty, this condition is called aoverflowo. this error is signaled in the bit err_rx of the syserr byte, and generates an interrupt it0 . to clear the error a cse 02 command must be issued. an overflow condition occurs when : - in synchronous mode: the host processor afor- getso to empty the current dtrbsx buffer. - in hdlc mode: when, while inside a frame, the host processors aforgetso to empty the current dtrbsx buffer. - in uart mode, this cannot happen. when an overflow condition occurs the host must restart the whole parallel initialisation. st75c530 - ST75C540 71/84
xii - receiving in parallel mode (continued) xii.5 - synchronous mode xii.5.1 - description in synchronous mode the st75c530/540 writes the received bit into the dual ram buffer without any modification. it starts with the bit 0 of the dtrbf0[0] byte. xii.5.2 - status word format thereceivestatus byte dtrbs0 or dtrbs1 have the same following meaning (see table below). the buff_leng is always 8 except when a lost of carrier ( sta_109 going to 0) happens. this status byte is set by the st75c530/540, just before generating the it3 interrupt. xii.6 - hdlc mode xii.6.1 - description in hdlc mode the st75c530/540 extracts from the received hdlc frame the data information only. it reports, trough the dual ram buffer, only data information and frame validity. the mecha- nism is as follows : - as long as the st75c530/540 receives continu- ous hdlc flag $7e, nothing happens. note that the st75c530/540 allows zero sharing between adjacent flags. - when the st75c530/540 receives some data, it removes inserted azeroo if needed, and starts to compute the crc. as soon as its internal buffer is full, the st75c530/540writes the received data into the dtrbfx buffer and sets the buff_sfrm inside the dtrbsx status byte. - when receiving additional data, the st75c530/540 feeds the buffer just like in syn- chronous mode. - when the st75c530/540 receives a closing flag (which can be shared with the following opening flag) it compares the received crc with its inter- nal computation. it writes the contents of the received last data into the dtrbfx buffer, sets the buff_efrm bit and reports any frame error in the dtrbsx register via the buff_errs bits. reported errors are : ? crc error (lowest priority): the received crc is not equal to the computed crc. some bits, inside the frame, are erroneous. ? non byte-aligned frame (middle priority): the received data bit count (after deletion of the azero insertedo), between the opening and the closing flag, is not a multiple of 8. ? aborted frame (highest priority): the frame was aborted with at least 7 consecutive a1o - an abort frame can be also detected, while in the inter frame mode, if instead of receiving $7e flag, the st75c530/540receive more than 7 consecu- tive a1o. in this case only one aborted frame is signaled, event if the o1o condition is maintained. dtrbsx in synchronous mode field pos. value definition buff_leng 3 .. 0 0 1 2 .. 8 other buffer empty. 1 byte received ( dtrbfx[0] ). 2 bytes received ( dtrbfx[0] and dtrbfx[1] ). .. 8 bytes received ( dtrbfx[0 .. 7] ). not used. other 7 .. 4 0 not used. xii.6.2 - status word format dtrbsx in hdlc mode field pos. value definition buff_leng 3 .. 0 0 1 2 .. 8 other buffer empty. 1 byte received ( dtrbfx[0] ). 2 bytes received ( dtrbfx[0] and dtrbfx[1] ). .. 8 bytes received ( dtrbfx[0 .. 7] ). not allowed. buff_errs 5 .. 4 0 0 01 10 11 no error. crc error. non byte-aligned frame. aborted frame. buff_sfrm 6 0 1 data stream. start of frame : the buffer is a beginning of frame. buff_efrm 7 0 1 data stream. end of frame : the buffer is a closing frame. st75c530 - ST75C540 72/84
xii - receiving in parallel mode (continued) xii.6.3 - single short frame received data buff_errs buff_sfrm buff_efrm buff_leng (buff_data) $7e d0 crc d1 d2 d3 062 8 $7e crc crc crc $7e $7e $7e d0 d1 d2 00 75c53050.eps figure 41 xii.6.4 - long frame received data buff_errs buff_sfrm buff_efrm buff_leng (buff_data) $7e 08 5 crc $7e d0 d1 d2 d3 0 8 d0 d1 d2 d3 8 (1) 75c53051.eps figure 42 note : 1. if error occurs during the reception, it is signaled in this last buffer. xii.6.5 - aborted frame received data buff_errs buff_sfrm buff_efrm buff_leng (buff_data ) $7e d0 d1 d2 d3 $7e d5 0 abort d4 d0 d1 d3 8 8x 8 x 11 75c53052.eps figure 43 st75c530 - ST75C540 73/84
xii - receiving in parallel mode (continued) xii.7 - uart mode xii.7.1 - description in uart mode the st75c530/540extracts from the received characters the data information only. it re- ports, troughthe dual ram buffer,onlydatainforma- tion character validity. the mechanism is as follows : - as long as the st75c530/540 receives continu- ous a1o nothing happens. - when the st75c530/540 receives the start bit (a0o) it starts to compute the parity. as soon as the number of data bit (defined by the form com- mand) is received, the st75c530/540 writes the received character into the dtrbfx buffer and update the receive status word dtrbsx. - the reported errors are : ? parity error (lowest priority): the received parity is not equal to the computed parity. some bits, inside the character, are erroneous. ? stop bit error (middle priority): the bit after the parity was not a stop bit (a1o). note that if the two stop bit format was selected, only the first stop bit will be checked. ? break detection (highest priority): the characteris a breaksignal as defined in the transmit section.if the duration of the break is longer than one char- acter, only one break bufferwill be reported. xi.7.2 - status word format dtrbsx in uart mode field pos. value definition buff_leng 3 .. 0 0 1 other buffer empty. 1 character received (dtrbfx[0]). not allowed. buff_errs 5..4 00 01 10 11 no error. parity error stop bit error break signal detected xiii - vocoder data exchange xiii.1 - overview the st75c530/540 can receive (or transmit) coded voice from (to) the telephone line or the audio interface. the receiving mode is the coder mode while the transmit is the decoder mode. two formats of voice compression are provided: low bit rate and adpcm. in all the formats and speed the managementof the coded voice is exactly the same. in any format a frame of all data equal to zero will be synthesised (decoder) as a frame of silence. xiii.2 - vocoder buffer a buffer area is reserved in the dual ram to exchange voice between the st75c530/540 and the host processor. thisareaisusedeitherforrecord- ing (coder) or playing back (decoder) the voice signal. the dual ram area associated with the vo- coder is as follows : name address description vocsta $1c vocoder buffer status vocdata $1d..$2e vocoder buffer data voccorr $2f..$30 vocoder buffer corrector the it1 interrupt signalis dedicatedto the vocoder buffer management. xiii.3 - transmit (decoder) this mode is entered with the conf decoder command. if the adpcm or low bit rate without error correc- tion mode (conf_ercor = 0) are selected, the user needs to feed the vocoder buffer with 18 bytes of voice data, then set the vocsta byte with a value different from zero. in the low bit rate with error mode (conf_ercor = 1), the user needsto feed the vocoder buffer with 20 bytes of voice data, then set the vocsta byte with a value different from zero. once the st75c530/540 have read the buffer, it clears the vocstabyte and raise the it1 interrupt. the it1 interrupt rate is as follows : mode interrupt time (ms) number of voice samples in the buffer (8khz sampling) adpcm 32kpbs 4.5 36 adpcm 24kpbs 6 48 adpcm 16kpbs 9 72 low bit rate nominal (with and without error correction) 30 240 low bit rate fast/slow playback depends on speed 15 to 45 depends on speed 120 to 360 low bit rate pause 0 - a silence can be generatedby writing zero to all the vocdata bytes (and voccorr bytes if conf_ercor = 1). the duration of the silence will be the same as the other frames of signal. as the buffer contains always a complete number of samples representing the same duration, it is easy to randomly advance forward/backward in a message. if the user does not feed the buffer within the interrupt time, the st75c530/540 will signal this error by rising the err_voco in thesyserrbyte and rising the it0 interrupt. in this case the pre- vious frame will be re-transmited. st75c530 - ST75C540 74/84
xiii.4 - receive (coder) this function can be entered either by : - the conf coder command. this corresponds to the anormal answering machineo function. - the modc command with modc_cod = 1, in the handset mode. this corresponds, in the handset mode to the aconversation record- ingo function. this reduced sub-mode does not allow adpcm format and does not perform vad (voice activity detector). once this function is selected, the st75c530/540 starts to code the voice signal, writes one frame of compressed voice into the vocdata bytes (if the low bit rate mode is selected, computes always the corrector bytes and writes them in the voccorr bytes)then writes the vocstabyte and generates the it1 interrupt. the it1 interrupt rate is as follows : mode interrupt time (ms) number of voice samples in the buffer (8khz sampling) adpcm 32kpbs 4.5 36 adpcm 24kpbs 6 48 adpcm 16kpbs 9 72 low bit rate (with and without error correction) 30 240 note that the voccorr are always computed, whatever the value of conf_ercor. the format of the vocsta byte is as follows : vocstat format field pos. value definition low bit rate voc _vad 70 1 vad unvoiced signal. vad voice signal. voc _num 4..0 10100 (20 decimal) number of vocdata bytes adpcm voc _vad 70 1 vad unvoiced signal. vad voice signal. voc _num 4..0 10010 (18 decimal) number of vocdata bytes note that in aconversation recordingo the vocsta byte is always $14. the user must read the vocdata (and optionally the voccorr) bytes and clear the vocsta byte (writing $00). if the user does not clear the vocsta byte within the interrupt time, the st75c530/540 will signal this error by rising the err_voco in the syserr byte and rising the it0 interrupt. in this case the current frame is lost. if the conf_supsil bit is 1 in the conf coder command, the interrupts it1 appears only when the vad has detected a voiced signal. xiii - vocoder data exchange (continued) st75c530 - ST75C540 75/84
xiv - transparent mode data exchange the mode uses the dpr locations to exchange samples between the host and the afe's. to allow maximum interrupt latency, the dsp uses internal buffers to store samples and updates the dpr buffers when internal buffers are ready. the dpr buffers are bidirectional, thus doubling the effective dpr capacity. the transfer mechanism is depicted below : 1. at baud rate (every 4 samples at 9.6khz), the dsp transfers 4 samples from the modem afe to the internal receive buffer, after sending them through a high-passfilter with a transferfunction h(z) = (z-1)/ (z-0.875) used to remove all dc components from the signal, and transfers 4 samplesfrom the internal transmit bufferto the modem afe. this comes from the currently implemented internal scheduling. the same operation is performed for the voice afe. 2. after 3 bauds, the internal receive buffer is full (the internal transmit buffer is also empty), the dpr buffer is copied to the internal transmit buffer, then the internal receive buffer is copied into the dpr. 3. a host interrupt is generated : during servicing, the host reads the dpr sample buffer then writes it with new transmitted samples. xiv.1 - sample buffers the mode uses the dpr locations to exchange samples between the host and the afe's ; since no data transfer (hdlc, uart) occurs in this mode, the full 0x10 .. 0x3f dpr locations are available. the modem sample buffer (modemdpr) uses locations 0x10 to 0x27 (24 bytes) to exchange 12 mafe samples. the audio sample buffer (audiodpr) uses locations 0x28 to 0x3f to ex- change 12 vafe samples. samples are repre- sented in 16-bit linear data format, byte order is little-endian (intel-like, lsbyteat low address),and consecutive locations correspond to consecutive samples in time. example : locations (0x10, 0x11) correspond to the first sample (lsb, msb) re- ceived from the line afe. xiv.2 - interrupts the dsp signal events to the host using the inter- rupt mailbox (itrest[0..6], itmask, itsrcr). it2 is set by the dsp whenever the dpr buffers are ready. this interrupt source can be masked through itmask, and acknowledged using itsrcr[0..6]. the host interrupt service routine should read received samples from the dpr, write transmitted samples to the dpr, then acknow- ledge by clearing the it2 flag. the interrupt latency is approximately equal to the interrupt period, i.e. t = 1/800 = 1.25ms. overrun and underrun condi- tions may occur if the host interrupt latency ex- ceeds the previous value. since this situation is unrecoverable, no specific action is taken. never- theless, for debug purposes the user can detect this condition by probing the interrupt line (sintr), and trigger on a pulse width greater than the maxi- mum allowed latency. st75c530 - ST75C540 76/84
xv - default call progress tone detectors 0 -10 -20 -30 -40 -50 0 200 400 600 800 1000 db no detection detection step = 10hz reference level = 0db f (hz) 75c53053.eps figure 44 : call progress tone detector band 1 0 -10 -20 -30 -40 -50 2000 2040 2080 2120 2160 2200 f (hz) no detection detection db reference level = 0db step = 10hz 75c53055.eps figure 46 : 2100hz answer tone detector 0 -10 -20 -30 -40 -50 200 320 440 560 680 800 f (hz) no detection detection db step = 10hz reference level = 0db 75c53056.eps figure 47 : 440hz tone detector 0 -8 -16 -24 -32 -40 0 720 1440 2160 2880 3600 f (hz) no detection detection db step = 100hz reference level = 0db 75c53054.eps figure 45 : call progress tone detector band 2 xvi - default answer tone detectors st75c530 - ST75C540 77/84
xvii - electrical schematics st75c530 ST75C540 1 2 3 4 5 6 7 8 9 10 16 17 18 19 20 11 12 13 14 15 60 59 58 57 56 55 54 53 52 51 45 44 43 42 41 50 49 48 47 46 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 gio00 ring relay0 rgnd int/mot scs sintr relay1 gio01 gio02 gio03 gio04 gio05 gio06 gio07 dv dd3 dgnd3 dv dd4 dgnd4 gio10 spk1n spk1p agndta v refn v refp v cm agndra mic1 mic2 mic3 av ddm agndm txa2 txa1 eyex eyey rxa dgnd6 dv dd6 dgnd1 sa6 sa5 sa4 sa3 sa2 sa1 sa0 sds sr/w dv dd2 dgnd2 dv dd1 sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 gio11 gio12 gio13 gio14 gio15 gio16 gio17 clkout dgnd5 dv dd 5 xtall extall test0 reset spk3n spk3p spk2n spk2p av dda xpll c14 (1) 100nf c13 (1) 100nf c15 10 m f c12 (1) 100nf v cc c3 (1) 100nf c1 2.2 m f v cc c10 (1) 100nf c11 4.7 m f c2 2.2 m f c16 (1) 100nf c6 2.2 m f c4 2.2 m f c7 (1) 100nf c5 (1) 100nf r1 1.2k w r2 1.2k w r3 1.2k w c17 (1) 2.2nf r4 1.2k w c18 (1) 2.2nf c19 (1) 2.2nf c20 (1) 2.2nf c8 4.7 m f c9 (1) 100nf mic1 mic2 mic3 rxa 0va v cm +5va agndm agndra 75c53057.eps figure 48 st75c530 - ST75C540 78/84
xviii - pcb design guidelines performances of the fax modem depends on the st75c530/540 intrinsic performances and on the proper pc board layout. all aspects of the proper engineering practices, for pc board design, are beyond the scope of this paragraph. we recommend the following points : - in a 4-layer pc board : separated digital ground and analog ground, connected together at one point, as close as possible to the st75c530/540, - in a 2-layer pc board : provide a ground grid in all spacearoundandundercomponentson bothsides of the band and connect to avoid small islands, - both agndr and agndt must be connected with very low impedance to a single point, (see chapter i.6, power supply), - the four 2.2nf capacitors connected to the rxa and mic1, mic2, mic3 pins must be as close as possible to them, - thetwo100nfcapacitorsconnectedtothev refp and v refn pins must be as close as possible to them, - analog and digital supplies must be connected together,at a single point, as close as possibleto the chip. 15 adc mute dac line hybrid txa1 txa2 rxa adc 14 11 10 mic3 8 mic1 9 mic2 79 spk2 78 mute 77 spk3 76 mute 2 spk1 1 mute [0..-30]db step 3db dac att_spk att_loc att_tx 4 tones generator dg dtmf detector 16 tone detectors 4 tone detectors v.21 flag detector ring detector dual ram interface dg programmable attenuation addition of signals automatic gain 75c53058.eps figure 49 : tone mode (tone) 15 adc mute dac line hybrid txa1 txa2 rxa adc 14 11 10 mic3 8 mic1 9 mic2 79 spk2 78 mute 77 spk3 76 mute 2 spk1 1 mute [0..-30]db step 3db dac att_spk att_loc att_tx 4 tones generator dg dtmf detector 6 tone detectors 4 tone detectors v.21 flag detector uart dual ram interface dg programmable attenuation addition of signals automatic gain ring detector v.23 demodulator 75c53059.eps figure 50 : tone mode with caller id (tonecid) xix - appendix a : modes of operation st75c530 - ST75C540 79/84
xix - appendix a : modes of operation (continued) dual ram interface 15 adc mute dac line hybrid txa1 txa2 rxa adc 14 11 10 mic3 8 mic1 9 mic2 79 spk2 78 mute 77 spk3 76 mute 2 spk1 1 mute [0..-30]db step 3db dac att_loc att_tx fax transmitter dg fax receiver 4 tone detectors v.21 flag detector dg programmable attenuation addition of signals automatic gain dtmf detector (v.21ch2 only) handshake and status report hdlc rx hdlc tx 42 sintr sd[0..7] 75c53060.eps figure 51 : fax modem mode (modem) echo canceller dual ram interface 15 adc mute dac line hybrid txa1 txa2 rxa adc 14 11 10 mic3 8 mic1 9 mic2 79 spk2 78 mute 77 spk3 76 mute 2 spk1 1 mute [0..-30]db step 3db dac att_loc att_tx modem transmitter modem receiver dg programmable attenuation addition of signals automatic gain handshake and status report 42 sintr sd[0..7] uart hdlc rx uart hdlc tx 75c53061.eps figure 52 : data modem mode (full duplex modem) (ST75C540 only) st75c530 - ST75C540 80/84
xix - appendix a : modes of operation (continued) 15 adc mute dac line hybrid txa1 txa2 rxa adc 14 11 10 mic3 8 mic1 9 mic2 79 spk2 78 mute 77 spk3 76 mute 2 spk1 1 mute [0..-30]db step 3db dac att_mic dg voice activity detector ring detector dual ram interface dg programmable attenuation addition of signals automatic gain att_sel att_loc 4 tone detectors dtmf detector agc coder 4 tone generators 75c53063.eps figure 54 : coder mode (coder) dual ram interface 15 adc mute dac line hybrid txa1 txa2 rxa adc 14 11 10 mic3 8 mic1 9 mic2 79 spk2 78 mute 77 spk3 76 mute 2 spk1 1 mute [0..-30]db step 3db dac att_loc att_tx dg 4 tone detectors dg programmable attenuation addition of signals automatic gain dtmf detector line echo canceller ring detector decoder 4 tone generators 75c53062.eps figure 53 : decoder mode (decoder) st75c530 - ST75C540 81/84
xix - appendix a : modes of operation (continued) dg agc dual ram interface 4 tone * detectors agc coder 4 tone * generator * default is 2. ring detector 15 adc mute dac line hybrid txa1 txa2 rxa adc 14 11 10 mic3 8 mic1 9 mic2 79 spk2 78 mute 77 spk3 76 mute 2 spk1 1 mute [0..-30]db step 3db dac att_mic half/full duplex speaker-phone algorithms att_tx 75c53065.eps figure 56 : telephone mode (handset) 15 adc mute dac line hybrid txa1 txa2 rxa adc 14 11 10 mic3 8 mic1 9 mic2 79 spk2 78 mute 77 spk3 76 mute 2 spk1 1 mute [0..-30]db step 3db dac att_mic dg dg programmable attenuation addition of signals automatic gain 4 tone detectors dtmf detector agc line echo canceller dual ram interface att_tx 75c53064.eps figure 55 : room monitoring mode (room) st75c530 - ST75C540 82/84
xix - appendix a : modes of operation (continued) 15 adc mute dac line hybrid txa1 txa2 rxa adc 14 11 10 mic3 8 mic1 9 mic2 79 spk2 78 mute 77 spk3 76 mute 2 spk1 1 mute [0..-30]db step 3db dac dg programmable attenuation addition of signals automatic gain att_mic dc- blocka dc- block att_spk att_loc dg 6 primary tone detectors dtmf detector 4 secondary tone detectors 4 tone generators att_modrx att_modtx att_tx att_audtx att_audrx dual ram interface att_sel (*) (*) (*) h(z) = z-1 z - 0.875 75c53066.eps figure 57 : transparentmode st75c530 - ST75C540 83/84
80 61 d3 21 40 1 20 e c b a1 a2 a d1 d 41 60 e3 e1 e l k l1 0,25 mm .010 inch gage plane 0,10 mm .004 inch seating plane pm-1s.eps xx - package mechanical data 80 pins - full thin plastic quad flat pack (tqfp) dimensions millimeters inches min. typ. max. min. typ. max. a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.22 0.32 0.38 0.010 0.012 0.014 c 0.09 0.20 0.004 0.008 d 16.00 0.630 d1 14.00 0.551 d3 12.35 0.486 e 0.65 0.026 e 16.00 0.630 e1 14.00 0.551 e3 12.35 0.486 l 0.45 0.60 0.75 0.020 0.024 0.030 l1 1.00 0.039 k0 o (min.), 7 o (max.) 1s.tbl information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no licence is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical comp onents in lifesupport devicesor systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 1999 stmicroelectronics - all rights reserved purchase of i 2 c components of stmicroelectronics, conveys a license under the philips i 2 c patent. rights to use these components in a i 2 c system, is granted provided that the system conforms to the i 2 c standard specifications as defined by philips. stmicroelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the netherlands singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. http://www.st.com st75c530 - ST75C540 84/84

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